Datasheet

408
AT32UC3A
external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
1: Byte write access type:
Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
Read operation is controlled using NCS and NRD.
0: Byte select access type:
Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
WRITE_MODE
1: The write operation is controlled by the NWE signal.
If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal.
If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
READ_MODE:
1: The read operation is controlled by the NRD signal.
Data Bus Width (DBW)
DBW Data Bus Width
0 0 8-bit bus
0 1 16-bit bus
1 0 32-bit bus
1 1 Reserved
Table 27-9. EXNW_MODE
EXNW_MODE NWAIT Mode
0 0 Disabled
0 1 Reserved
1 0 Frozen Mode
1 1 Ready Mode
32058K
AVR32-01/12