Datasheet

397
AT32UC3A
27.6.7.4 NWAIT Latency and Read/write Timings
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1
cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT
signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Fig-
ure 27-31.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the
read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
Figure 27-31. NWAIT Latency
Wait STATE
012
3
4
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
NRD
NWAIT
nternally synchronized
NWAIT signal
Minimal pulse length
00
NWAIT latency 2 cycle resynchronization
Read cycle
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
32058K
AVR32-01/12