Datasheet

391
AT32UC3A
• read access followed by a write access on the same chip select,
with no TDF optimization.
Figure 27-24. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
selects.
Figure 27-25. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects.
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Read2 controlling
signal(NRD)
D[15:0]
Read1 hold = 1
Read1 cycle
TDF_CYCLES = 6
Chip Select Wait State
5 TDF WAIT STATES
TDF_CYCLES = 6
Read2 setup = 1
Read 2 cycle
TDF_MODE=0
(optimization disabled)
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Write2 controlling
signal(NWE)
D[15:0]
Read1 cycle
TDF_CYCLES = 4
Chip Select
Wait State
Read1 hold = 1
TDF_CYCLES = 4
Read to Write
Wait State
2 TDF WAIT STATES
Write2 setup = 1
Write 2 cycle
TDF_MODE=0
(optimization disabled)
32058K
AVR32-01/12