Datasheet

384
AT32UC3A
Figure 27-17. Chip Select Wait State between a Read Access on NCS0 and a Write Access on
NCS2
CLK_SMC
A[25:2]
S0, NBS1,
A0, A1
NRD
NWE
NCS0
NCS2
D[15:0]
NRD_CYCLE
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
32058K
AVR32-01/12