Datasheet

377
AT32UC3A
Figure 27-11. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
– Read is Controlled by NCS (READ_MODE = 0)
Figure 27-12 shows the typical read cycle of an LCD module. The read data is valid t
PACC
after
the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be
sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled
by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates
the rising edge of NCS, whatever the programmed waveform of NRD may be.
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
t
PACC
Data Sampling
32058K
AVR32-01/12