Datasheet

339
AT32UC3A
26.8 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) User Interface
26.8.1 Register Mapping
3. Values in the Version Register vary with the version of the IP block implementation.
Table 26-12. Register Mapping
Offset Register Name Access Reset
0x0000 Control Register CR Write-only –
0x0004 Mode Register MR Read-write –
0x0008 Interrupt Enable Register IER Write-only –
0x000C Interrupt Disable Register IDR Write-only –
0x0010 Interrupt Mask Register IMR Read-only 0x0
0x0014 Channel Status Register CSR Read-only –
0x0018 Receiver Holding Register RHR Read-only 0x0
0x001C Transmitter Holding Register THR Write-only –
0x0020 Baud Rate Generator Register BRGR Read-write 0x0
0x0024 Receiver Time-out Register RTOR Read-write 0x0
0x0028 Transmitter Timeguard Register TTGR Read-write 0x0
0x2C - 0x3C Reserved – – –
0x0040 FI DI Ratio Register FIDI Read-write 0x174
0x0044 Number of Errors Register NER Read-only –
0x0048 Reserved – – –
0x004C IrDA Filter Register IFR Read-write 0x0
0x0050 Manchester Encoder Decoder Register MAN Read-write 0x30011004
0x5C - 0xF8 Reserved – – –
0xFC Version Register VERSION Read-only 0x–
(3)
0x5C - 0xFC Reserved – – –
32058K
AVR32-01/12