Datasheet

335
AT32UC3A
Figure 26-38. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Figure 26-39. SPI Transfer Format (CPHA=0, 8 bits per transfer)
26.7.8.4 Receiver and Transmitter Control
See Section “26.7.2” on page 309.
CLK cycle (for reference)
CLK
(CPOL= 1)
MOSI
SPI Master ->TXD
SPI Slave ->RXD
MISO
SPI Master ->RXD
SPI Slave ->TXD
NSS
SPI Master ->RTS
SPI Slave ->CTS
MSB
MSB
1
CLK
(CPOL= 0)
3
5
6
7 8
LSB
1234
6
6 5
5
4 3
2 1
LSB
2 4
CLK cycle (for reference)
CLK
(CPOL= 0)
CLK
(CPOL= 1)
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
MSB 6 5
MSB 6 5
4
4 3
3 2
2 1
1
LSB
LSB
87654321
32058K
AVR32-01/12