Datasheet

283
AT32UC3A
• CKG: Transmit Clock Gating Selection
• CKI: Transmit Clock Inversion
0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
• CKO: Transmit Clock Output Mode Selection
• CKS: Transmit Clock Selection
CKG Transmit Clock Gating
0x0 None, continuous clock
0x1 Transmit Clock enabled only if TX_FRAME_SYNC Low
0x2 Transmit Clock enabled only if TX_FRAME_SYNC High
0x3 Reserved
CKO Transmit Clock Output Mode TX_CLOCK pin
0x0 None Input-only
0x1 Continuous Transmit Clock Output
0x2 Transmit Clock only during data transfers Output
0x3-0x7 Reserved
CKS Selected Transmit Clock
0x0 Divided Clock
0x1 RX_CLOCK Clock signal
0x2 TX_CLOCK Pin
0x3 Reserved
32058K
AVR32-01/12