Datasheet

277
AT32UC3A
25.9.2 Clock Mode Register
Name: CMR
Access Type: Read/Write
Offset: 0x04
Reset value: 0x00000000
• DIV: Clock Divider
0: The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is CLK_SSC/2.
The minimum bit rate is CLK_SSC/2 x 4095 = CLK_SSC/8190.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – DIV
7 6 5 4 3 2 1 0
DIV
32058K
AVR32-01/12