Datasheet

275
AT32UC3A
25.9 User Interface
Table 25-4. Register Mapping
Offset Register Register Name Access Reset
0x0 Control Register CR Write –
0x4 Clock Mode Register CMR Read/Write 0x0
0x8 Reserved – – –
0xC Reserved – – –
0x10 Receive Clock Mode Register RCMR Read/Write 0x0
0x14 Receive Frame Mode Register RFMR Read/Write 0x0
0x18 Transmit Clock Mode Register TCMR Read/Write 0x0
0x1C Transmit Frame Mode Register TFMR Read/Write 0x0
0x20 Receive Holding Register RHR Read 0x0
0x24 Transmit Holding Register THR Write –
0x28 Reserved – – –
0x2C Reserved – – –
0x30 Receive Sync. Holding Register RSHR Read 0x0
0x34 Transmit Sync. Holding Register TSHR Read/Write 0x0
0x38 Receive Compare 0 Register RC0R Read/Write 0x0
0x3C Receive Compare 1 Register RC1R Read/Write 0x0
0x40 Status Register SR Read 0x000000CC
0x44 Interrupt Enable Register IER Write –
0x48 Interrupt Disable Register IDR Write –
0x4C Interrupt Mask Register IMR Read 0x0
0x50-0xFC Reserved – – –
32058K
AVR32-01/12