Datasheet

251
AT32UC3A
24.14.6 TWI Clock Waveform Generator Register
Name: CWGR
Access: Read-write
Reset Value: 0x00000000
CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
CKDIV
15 14 13 12 11 10 9 8
CHDIV
7 6 5 4 3 2 1 0
CLDIV
T
low
CLDIV( 2
CKDIV
×( ) 4)+ T
MCK
×=
T
high
CHDIV( 2
CKDIV
×( ) 4)+ T
MCK
×=
32058K
AVR32-01/12