Datasheet

156
AT32UC3A
21.4.9 Priority
If more then one PDCA channel is requesting transfer at a given time, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel 0 the highest priority.
21.4.10 Error Handling
If the memory address is set to point to an invalid location in memory, an error will occur when
the PDCA tries to perform a transfer. When an error occurs, the Transfer Error flag (TERR) in
the Interrupt Status Register will be set and the DMA channel that caused the error will be
stopped. In order to restart the channel, the user must program the Memory Address Register to
a valid address and then write the Error Clear bit (ECLR) in the Control Register (CR) to ‘1’. An
interrupt can optionally be triggered on errors by writing the TERR-bit in the Interrupt Enable
Register (IER) to ‘1’.
21.5 User Interface
21.5.1 Memory Map Overview
Note: The number of channels is implementation specific. See part documentation for details.
21.5.2 Channel Memory Map
Table 21-1. Register Map Overview
Address Range Contents
0x0000 - 0x003F DMA channel 0 configuration registers
0x0040 - 0x007F DMA channel 1 configuration registers
0x0080 - 0x00BF DMA channel 2 configuration registers
0x00C0 - 0x00FF DMA channel 3 configuration registers
0x0100 - 0x013F DMA channel 4 configuration registers
- -
- DMA channel n-1 configuration registers
Offset Register Register Name Access Reset
0x00 Memory Address Register MAR Read/Write 0x00000000
0x04 Peripheral Select Register PSR Read/Write *
0x08 Transfer Counter Register TCR Read/Write 0x00000000
0x0C Memory Address Reload Register MARR Read/Write 0x00000000
0x10 Transfer Counter Reload Register TCRR Read/Write 0x00000000
0x14 Control Register CR Write-only -
0x18 Mode Register MR Read/Write 0x00000000
0x1C Status Register SR Read-only 0x00000000
0x20 Interrupt Enable Register IER Write-only -
32058K
AVR32-01/12