Datasheet

148
AT32UC3A
20.5 Application Example
20.5.1 Hardware Interface
Table 20-3 on page 148 details the connections to be applied between the EBI pins and the
external devices for each Memory Controller.
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. BEx: Byte x Enable (x = 0,1,2 or 3)
A[22:15] Not Supported SMC_A[22:15]
A[23] Not Supported SMC_A[23]
D[15:0] D[15:0] D[15:0]
Table 20-2. EBI Pins and Memory Controllers I/O Lines Connections
EBI Pins SDRAMC I/O Lines SMC I/O Lines
Table 20-3. EBI Pins and External Static Devices Connections
Signals Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
Controller SMC
D0 - D7 D0 - D7 D0 - D7 D0 - D7
D8 - D15 – D8 - D15 D8 - D15
A0/NBS0 A0 – NLB
A1/NWR2/NBS2 A1 A0 A0
A2 - A22 A[2:22] A[1:21] A[1:21]
A23 A[23] A[22] A[22]
NCS0 CS CS CS
NCS1/SDCS0 CS CS CS
NCS2 CS CS CS
NCS3 CS CS CS
NRD/NOE OE OE OE
NWR0/NWE WE WE
(1)
WE
NWR1/NBS1 – WE
(1)
NUB
NWR3/NBS3 – – –
32058K
AVR32-01/12