Datasheet

101
AT32UC3A
pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
16.4 User Interface
This chapter lists the INTC registers are accessible through the PB bus. The registers are used
to control the behaviour and read the status of the INTC.
16.4.1 Memory Map
The following table shows the address map of the INTC registers, relative to the base address of
the INTC.
16.4.2 Interrupt Request Map
The mapping of interrupt requests from peripherals to INTREQs is presented in the Peripherals
Section.
Table 16-1. INTC address map
Offset Register Name Access Reset Value
0 Interrupt Priority Register 0 IPR0 Read/Write 0x0000_0000
4 Interrupt Priority Register 1 IPR1 Read/Write 0x0000_0000
... ... ... ... ...
252 Interrupt Priority Register 63 IPR63 Read/Write 0x0000_0000
256 Interrupt Request Register 0 IRR0 Read-only N/A
260 Interrupt Request Register 1 IRR1 Read-only N/A
... ... ... ... ...
508 Interrupt Request Register 63 IRR63 Read-only N/A
512 Interrupt Cause Register 3 ICR3 Read-only N/A
516 Interrupt Cause Register 2 ICR2 Read-only N/A
520 Interrupt Cause Register 1 ICR1 Read-only N/A
524 Interrupt Cause Register 0 ICR0 Read-only N/A
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AVR32-01/12