Features • High Performance, Low Power 32-Bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing 1.
AT32UC3A • On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins) • 5V Input Tolerant I/Os • Single 3.3V Power Supply or Dual 1.8V-3.
AT32UC3A 1. Description The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.
AT32UC3A 2. Configuration Summary The table below lists all AT32UC3A memory and package configurations: Device Flash SRAM Ext.
AT32UC3A 4. Blockdiagram C ON FIGU RATIO N HSB-PB BRIDG E B EXTERNAL INTERRUPT CO NTRO LLER REAL TIM E CO UNTER W ATCHDO G TIM ER 115 kHz RCO SC XIN 32 XO UT32 XIN0 XO U T0 XIN1 XO U T1 32 KHz O SC O SC0 O SC1 PLL0 PLL1 RESET_N G CLK[3..0] A[2..0] B[2..0] CLK[2..
AT32UC3A 4.1 4.1.1 Processor and architecture AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture. – – – – – 15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file. Fully orthogonal instruction set. Privileged and unprivileged modes enabling efficient and secure Operating Systems. Innovative instruction set together with variable instruction length ensuring industry leading code density.
AT32UC3A • Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus Figure 4-1 gives an overview of the bus system. All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the High Speed Bus, and which DMA controller is connected to which peripheral.
AT32UC3A 5. Signals Description The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in ”Peripheral Multiplexing on I/O lines” on page 45. Table 5-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDPLL Power supply for PLL Power Input 1.65V to 1.95 V VDDCORE Core Power Supply Power Input 1.65V to 1.95 V VDDIO I/O Power Supply Power Input 3.0V to 3.
AT32UC3A Table 5-1.
AT32UC3A Table 5-1.
AT32UC3A Signal Description List Table 5-1.
AT32UC3A Table 5-1. Signal Description List Signal Name Function Type Active Level Comments Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input ADVREF Analog positive reference voltage input Analog input 2.6 to 3.
AT32UC3A 6. Power Considerations 6.1 Power Supplies The AT32UC3A has several types of power supply pins: • • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. VDDANA: Powers the ADC Voltage is 3.3V nominal. VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal. VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. VDDPLL: Powers the PLL. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO, VDDPLL. The ground pin for VDDANA is GNDANA.
AT32UC3A 6.2 6.2.1 Voltage Regulator Single Power Supply The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to the 1.8V domains. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip.
AT32UC3A 6.3 Analog-to-Digital Converter (A.D.C) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. 3.3V ADVREF C VREF2 C VREF1 Refer to Section 38.4 on page 765 for decoupling capacitors values and electrical characteristics. In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption.
AT32UC3A 7. Package and Pinout The device pins are multiplexed with peripheral functions as described in ”Peripheral Multiplexing on I/O lines” on page 45. TQFP100 Pinout Figure 7-1. 75 51 76 50 100 26 1 25 TQFP100 Package Pinout Table 7-1.
AT32UC3A TQFP100 Package Pinout Table 7-1. 23 PA02 48 DM 73 PB05 98 PB17 24 PA03 49 DP 74 PB06 99 PB18 25 PA04 50 GND 75 PB07 100 PB19 LQFP144 Pinout Figure 7-2. 108 73 109 72 144 37 1 36 VQFP144 Package Pinout Table 7-2.
AT32UC3A VQFP144 Package Pinout Table 7-2.
AT32UC3A Table 7-3. BGA144 Package Pinout A1..
AT32UC3A 8. I/O Line Considerations 8.1 JTAG pins TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. 8.2 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 8.
AT32UC3A 9. Processor and Architecture This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 9.
AT32UC3A A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions.
AT32UC3A The AVR32UC Pipeline Figure 9-2. MUL IF ID Pref etch unit Decode unit Regf ile Read A LU LS 9.2.2 Multiply unit Regf ile w rite A LU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
AT32UC3A The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 9-1. 9.2.6 Instructions with unaligned reference support Instruction Supported alignment ld.d Word st.
AT32UC3A 9.3 9.3.1 Programming Model Register file configuration The AVR32UC register file is shown below. The AVR32UC Register File Figure 9-3. 9.3.
AT32UC3A Figure 9-5. The Status Register Low Halfword Bit 15 Bit 0 R T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Register Remap Enable 9.3.3 Processor States 9.3.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 9-2 on page 26. Table 9-2. Overview of execution modes, their priorities and privilege levels.
AT32UC3A All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 9.3.4 System registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions.
AT32UC3A Table 9-3.
AT32UC3A Table 9-3. 9.
AT32UC3A The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 9.4.2 Exceptions and interrupt requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked.
AT32UC3A status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability.
AT32UC3A Priority and handler addresses for events Table 9-4.
AT32UC3A 10. Memories 10.
AT32UC3A Table 10-2. Flash Memory Parameters Part Number Flash Size (FLASH_PW) Number of pages (FLASH_P) Page size (FLASH_W) General Purpose Fuse bits (FLASH_F) AT32UC3A0512 512 Kbytes 1024 128 words 32 fuses AT32UC3A1512 512 Kbytes 1024 128 words 32 fuses AT32UC3A0256 256 Kbytes 512 128 words 32 fuses AT32UC3A1256 256 Kbytes 512 128 words 32 fuses AT32UC3A1128 128 Kbytes 256 128 words 32 fuses AT32UC3A0128 128 Kbytes 256 128 words 32 fuses 10.
AT32UC3A Figure 10-1.
AT32UC3A 11. Fuses Settings The flash block contains a number of general purpose fuses. Some of these fuses have defined meanings outside the flash controller and are described in this section. The general purpose fuses are erase by a JTAG chip erase. 11.1 Flash General Purpose Fuse Register (FGPFRLO) Table 11-1.
AT32UC3A LOCK, EPFL, BOOTPROT These are Flash controller fuses and are described in the FLASHC section. 11.2 Default Fuse Value The devices are shipped with the FGPFRLO register value: 0xFC07FFFF: • GPF31 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader. • GPF30 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader. • GPF29 fuse set to 1b. This fuse is used by the pre-programmed USB bootloader. • BODEN fuses set to 11b. BOD is disabled. • BODHYST fuse set to 1b.
AT32UC3A 12. Peripherals 12.1 Peripheral address map Table 12-1.
AT32UC3A Table 12-1. Peripheral Address Mapping (Continued) Address 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 12.
AT32UC3A The following GPIO registers are mapped on the local bus: Table 12-2.
AT32UC3A Table 12-2. Local bus mapped GPIO registers Port Register Mode Local Bus Address Access 3 Output Driver Enable Register (ODER) WRITE 0x4000_0340 Write-only SET 0x4000_0344 Write-only CLEAR 0x4000_0348 Write-only TOGGLE 0x4000_034C Write-only WRITE 0x4000_0350 Write-only SET 0x4000_0354 Write-only CLEAR 0x4000_0358 Write-only TOGGLE 0x4000_035C Write-only - 0x4000_0360 Read-only Output Value Register (OVR) Pin Value Register (PVR) 12.
AT32UC3A Table 12-3.
AT32UC3A Table 12-3. Interrupt Request Signal Map 9 0 Serial Peripheral Interface SPI0 10 0 Serial Peripheral Interface SPI1 11 0 Two-wire Interface TWI 12 0 Pulse Width Modulation Controller PWM 13 0 Synchronous Serial Controller SSC 0 Timer/Counter TC0 1 Timer/Counter TC1 2 Timer/Counter TC2 15 0 Analog to Digital Converter ADC 16 0 Ethernet MAC MACB 17 0 USB 2.0 OTG Interface USBB 18 0 SDRAM Controller 19 0 Audio Bitstream DAC 14 12.
AT32UC3A 12.4.3 SPIs Each SPI can be connected to an internally divided clock: Table 12-6. SPI clock connections SPI Source Name Connection 0 Internal CLK_DIV PBA clock or PBA clock / 32 1 12.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register.
AT32UC3A Table 12-8. 12.7 PDC Handshake Signals PID Value Peripheral module & direction 4 USART2 - RX 5 USART3 - RX 6 TWI - RX 7 SPI0 - RX 8 SPI1 - RX 9 SSC - TX 10 USART0 - TX 11 USART1 - TX 12 USART2 - TX 13 USART3 - TX 14 TWI - TX 15 SPI0 - TX 16 SPI1 - TX 17 ABDAC Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C.
AT32UC3A Table 12-9.
AT32UC3A Table 12-9.
AT32UC3A Table 12-9. 12.
AT32UC3A 12.10 GPIO The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device. 12.11 Peripheral overview 12.11.
AT32UC3A – Supports Mobile SDRAM Devices • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • CAS Latency of 1, 2, 3 Supported • Auto Precharge Command Not Used 12.11.4 USB Controller 12.11.5 • USB 2.
AT32UC3A – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.
AT32UC3A 12.11.11 Ethernet 10/100 MAC • • • • • • • • • • • • Compatibility with IEEE Standard 802.
AT32UC3A 13. Power Manager (PM) Rev: 2.0.0.1 13.1 Features • • • • • • • • • • • • • 13.
AT32UC3A 13.
AT32UC3A 13.4 Product Dependencies 13.4.1 I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the GPIO controller. 13.4.2 Interrupt The PM interrupt line is connected to one of the internal sources of the interrupt controller.
AT32UC3A The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in ”Interrupt Enable/Disable/Mask/Status/Clear” on page 76. C2 XO U T XIN C1 Figure 13-2. Oscillator connections 13.5.
AT32UC3A divide the output of the PLL by two and bring the clock in range of the max frequency of the CPU. When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable.
AT32UC3A 13.5.5 Synchronous clocks The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as fCPU fPBA,B,. The synchronous clock source can be changed on-the fly, responding to varying load in the application.
AT32UC3A caler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: fCPU = fmain / 2(CPUSEL+1) Similarly, the clock for the PBA, and PBB can be divided by writing their respective bitfields. To ensure correct operation, frequencies must be selected so that fCPU fPBA,B. Also, frequencies must never exceed the specified maximum frequency for each clock domain. CKSEL can be written without halting or disabling peripheral modules.
AT32UC3A 13.5.7 Sleep modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument. 13.5.7.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
AT32UC3A The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 13.5.7.3 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions.
AT32UC3A Sleep Controller 0 Osc0 clock Osc1 clock PLL0 clock PLL1 clock 0 Divider Mask Generic Clock 1 1 PLLSEL OSCSEL DIV DIVEN CEN Figure 13-5. Generic clock generation 13.5.8.1 Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
AT32UC3A 13.5.8.4 Generic clock implementation In AT32UC3A, there are 6 generic clocks. These are allocated to different functions as shown in Table 13-2. Table 13-2. Generic clock allocation Clock number 13.5.9 Function 0 GCLK0 pin 1 GCLK1 pin 2 GCLK2 pin 3 GCLK3 pin 4 USBB 5 ABDAC Divided PB clocks The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock.
AT32UC3A It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated. Table 13-4 lists these and other reset sources supported by the Reset Controller. RC _RCAUSE RESET_N P o w e r-O n D e te c to r CPU, HSB, PBA, PBB R eset C o n tro lle r B ro w n o u t D e te c to r O C D , R T C /W D T C lo c k G e n e ra to JT A G OCD W a tc h d o g R e s e t Figure 13-6.
AT32UC3A Table 13-4 lists parts of the device that are reset, depending on the reset source. Effect of the different reset events Table 13-4.
AT32UC3A 13.5.11.3 External Reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. 13.5.12 Calibration registers The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap voltage reference through several calibrations registers. Those calibration registers are loaded after a Power On Reset with default values stored in factory-programmed flash fuses.
AT32UC3A 0x0060 Generic Clock Control GCCTRL Read/Write 0x00000000 0x0064 - 0x00BC Reserved 0x00C0 RC Oscillator Calibration Register RCCR Read/Write Factory settings 0x00C4 Bandgap Calibration Register BGCR Read/Write Factory settings 0x00C8 Linear Regulator Calibration Register VREGCR Read/Write Factory settings 0x00CC Reserved 0x00D0 BOD Level Register BOD Read/Write BOD fuses in Flash 0x00D4 - 0x013C Reserved 0x0140 Reset Cause Register RCAUSE Read Only Latest Reset So
AT32UC3A 13.6.
AT32UC3A 13.6.2 Clock Select Name: CKSEL Access Type: Read/Write 31 30 29 28 27 PBBDIV - - - - 23 22 21 20 19 PBADIV - - - - 15 14 13 12 11 HSBDIV - - - - 7 6 5 4 3 CPUDIV - - - - 26 25 24 PBBSEL 18 17 16 PBASEL 10 9 8 HSBSEL 2 1 0 CPUSEL • PBBDIV, PBBSEL: PBB Division and Clock Select PBBDIV = 0: PBB clock equals main clock. PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1).
AT32UC3A 13.6.3 Clock Mask Name: CPU/HSB/PBA/PBBMASK Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode.
AT32UC3A Maskable module clocks in AT32UC3A. Table 13-5.
AT32UC3A 13.6.4 PLL Control Name: PLL0,1 Access Type: Read/Write 31 30 29 28 27 RESERVED 23 26 25 24 18 17 16 9 8 1 0 PLLOSC PLLEN PLLCOUNT 22 21 20 19 RESERVED 15 14 PLLMUL 13 12 11 10 RESERVED PLLDIV 7 6 5 - - - 4 3 PLLOPT 2 • RESERVED: Reserved bitfields Reserved for internal use. Always write to 0.
AT32UC3A Table 13-6. PLLOPT Fields Description in AT32UC3A Description PLLOPT[0]: VCO frequency 0 160MHz
AT32UC3A 13.6.
AT32UC3A 13.6.
AT32UC3A 13.6.
AT32UC3A The effect of writing or reading the bits listed above depends on which register is being accessed: • IER (Write-only) • • • • 0: No effect 1: Enable Interrupt IDR (Write-only) 0: No effect 1: Disable Interrupt IMR (Read-only) 0: Interrupt is disabled 1: Interrupt is enabled ISR (Read-only) 0: An interrupt event has not occurred or has been previously cleared 1: An interrupt event has not occurred ICR (Write-only) 0: No effect 1: Clear corresponding event 77 32058K AVR32-01/12
AT32UC3A 13.6.8 Power and Oscillators Status Name: POSCSR Access Type: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - BODDET 15 14 13 12 11 10 9 8 - - - - - - OSC32RDY OSC1RDY 7 6 5 4 3 2 1 0 OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0 • BODDET: Brown out detection 0: No BOD event 1: BOD has detected that power supply is going below BOD reference value.
AT32UC3A 13.6.9 Generic Clock Control Name: GCCTRL Access Type: Read/Write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 DIV[7:0] 7 6 5 4 3 2 1 0 - - - DIVEN - CEN PLLSEL OSCSEL There is one GCCTRL register per generic clock in the design. • DIV: Division Factor • DIVEN: Divide Enable 0: The generic clock equals the undivided source clock.
AT32UC3A 13.6.10 Reset Cause Name: RCAUSE Access Type: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - JTAGHARD OCDRST 7 6 5 4 3 2 1 0 CPUERR - - JTAG WDT EXT BOD POR • POR Power-on Reset The CPU was reset due to the supply voltage being lower than the power-on threshold level.
AT32UC3A 13.6.11 BOD Control BOD Level register Register name BOD Register access Read/Write 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - HYST CTRL 1 0 LEVEL • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A 13.6.12 RC Oscillator Calibration Register name RCCR Register access Read/Write 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 CALIB 1 0 CALIB • CALIB: Calibration Value Calibration Value for the RC oscillator.
AT32UC3A 13.6.13 Bandgap Calibration Register name BGCR Register access Read/Write 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. • CALIB: Calibration value Calibration value for Bandgap.
AT32UC3A 13.6.14 PM Voltage Regulator Calibration Register Register name VREGCR Register access Read/Write 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - CALIB • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
AT32UC3A 13.6.15 General Purpose Low-power register 0/1 Register name GPLP0,1 Register access Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 GPLP 23 22 21 20 GPLP 15 14 13 12 GPLP 7 6 5 4 GPLP These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these registers untouched.
AT32UC3A 14. Real Time Counter (RTC) Rev: 2.3.0.1 14.1 Features • • • • 32-bit real-time counter with 16-bit prescaler Clocked from RC oscillator or 32 KHz oscillator High resolution: Max count frequency 16 KHz Long delays – Max timeout 272 years • Extremely low power consumption • Available in all sleep modes except Static • Interrupt on wrap 14.2 Description The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement of real-time sequences.
AT32UC3A 14.3 Block Diagram Figure 14-1. Real Time Counter module block diagram RTC_CTRL EN PCLR CLK32 32 kHz 1 RC OSC 0 RTC_TOP 16-bit Prescaler 32-bit counter TOPI IRQ RTC_VAL 14.4 Product Dependencies 14.4.1 Power Management The RTC is continuously clocked, and remains operating in all sleep modes except Static. Interrupts are not available in DeepStop mode. 14.4.2 Interrupt The RTC interrupt line is connected to one of the internal sources of the interrupt controller.
AT32UC3A The CLK32 bit selects either the RC oscillator or the 32 KHz oscillator as clock source for the prescaler. The PSEL bitfield selects the prescaler tapping, selecting the source clock for the RTC: fRTC = 2-(PSEL+1) * (fRC or 32 KHz) 14.5.1.2 Counter operation When enabled, the RTC will increment until it reaches TOP, and then wrap to 0x0. The status bit TOPI in ISR is set when this occurs. From 0x0 the counter will count TOP+1 cycles of the source clock before it wraps back to 0x0.
AT32UC3A 14.6 User Interface Offset Register Register Name Access Reset 0x00 RTC Control CTRL Read/Write 0x0 0x04 RTC Value VAL Read/Write 0x0 0x08 RTC Top TOP Read/Write 0x0 0x10 RTC Interrupt Enable IER Write-only 0x0 0x14 RTC Interrupt Disable IDR Write-only 0x0 0x18 RTC Interrupt Mask IMR Read-only 0x0 0x1C RTC Interrupt Status ISR Read-only 0x0 0x20 RTC Interrupt Clear ICR Write-only 0x0 14.6.
AT32UC3A • WAKE_EN: Wakeup enable 0: The RTC does not wake up the CPU from sleep modes 1: The RTC wakes up the CPU from sleep modes. • PCLR: Prescaler Clear Writing 1 to this strobe clears the prescaler.
AT32UC3A 14.6.2 RTC Value Name: VAL Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VAL[31:24] 23 22 21 20 VAL[23:16] 15 14 13 12 VAL[15:8] 7 6 5 4 VAL[7:0] • VAL: RTC Value This value is incremented on every rising edge of the source clock.
AT32UC3A 14.6.3 RTC Top Name: TOP Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TOP[31:24] 23 22 21 20 TOP[23:16] 15 14 13 12 TOP[15:8] 7 6 5 4 TOP[7:0] • TOP: RTC Top Value VAL wraps at this value.
AT32UC3A 14.6.4 RTC Interrupt Enable/Disable/Mask/Status/Clear Name: IER/IDR/IMR/ISR/ICR Access Type: IER/IDR/ICR: Write-only IMR/ISR: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TOPI • TOPI: Top Interrupt VAL has wrapped at its top value.
AT32UC3A 15. Watchdog Timer (WDT) Rev: 2.3.0.1 15.1 Features • Watchdog Timer counter with 16-bit prescaler • Clocked from RC oscillator 15.2 Description The Watchdog Timer (WDT) has a prescaler generating a timeout period. This prescaler is clocked from the RC oscillator. The watchdog timer must be periodically reset by software within the timeout period, otherwise, the device is reset and starts executing from the boot vector.
AT32UC3A 15.5 Functional Description The WDT is enabled by writing the EN bit in the CTRL register to one. This also enables the RC clock for the prescaler. The PSEL bitfield in the same register selects the watchdog timeout period: TWDT = 2(PSEL+1) / fRC The next timeout period will begin as soon as the watchdog reset has occured and count down during the reset sequence.
AT32UC3A 15.
AT32UC3A 15.6.1 WDT Control Name: CTRL Access Type: Read/Write 31 30 29 28 27 26 25 24 KEY[7:0] 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - 7 6 5 4 3 2 1 0 - - - - - - - EN PSEL • KEY This bitfield must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This bitfield always reads as zero. • PSEL: Prescale Select Prescaler bit PSEL is used as watchdog timeout period.
AT32UC3A 15.6.2 WDT Clear Name: CLR Access Type: Write-only When the watchdog timer is enabled, this register must be periodically written, with any value, within the watchdog timeout period, to prevent a watchdog reset.
AT32UC3A 16. Interrupt Controller (INTC) Rev: 1.0.1.1 16.1 Description The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable interrupts, and a Non-Maskable Interrupt (NMI). The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request lines, these lines are connected to the peripherals.
AT32UC3A oritize between them. All of the input lines in each group are logically-ORed together to form the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group. The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to INT3 by associating each group with the INTLEVEL field in the corresponding IPR register. The GrpReq inputs are then masked by the I0M, I1M, I2M, I3M and GM mask bits from the CPU status register.
AT32UC3A pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 16.4 User Interface This chapter lists the INTC registers are accessible through the PB bus. The registers are used to control the behaviour and read the status of the INTC. 16.4.1 Memory Map The following table shows the address map of the INTC registers, relative to the base address of the INTC.
AT32UC3A 16.4.3 Interrupt Request Registers Register Name: IRR0...
AT32UC3A 16.4.4 Interrupt Priority Registers Register Name: IPR0...
AT32UC3A 16.4.5 Interrupt Cause Registers Register Name: ICR0...ICR3 Access Type: Read-only 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 4 3 2 1 0 CAUSE • CAUSE: Interrupt group causing interrupt of priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n.
AT32UC3A 17. External Interrupts Controller (EIC) Rev: 2.3.0.2 17.1 Features • • • • • • • • 17.2 Dedicated interrupt requests for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Keypad scan support Maskable NMI interrupt Description The External Interrupt Module allows pins to be configured as external interrupts.
AT32UC3A 17.3 Block Diagram Figure 17-1. External Interrupt Module block diagram EIM_LEVEL EIM_MODE EIM_EDGE Polarity control EIM_EN EIM_DIS EXTINTn NMI Enable Asynchronus detector EIM_FILTER EIM_LEVEL EIM_MODE EIM_EDGE INTn Filter Edge/Level Detector EIM_ISR EIM_CTRL EIM_IER EIM_IDR EIM_ICR Wake detect Mask IRQn EIM_IMR EIM_WAKE RC clk Prescaler PRESC Shifter EN SCAN PIN EIM_SCAN 17.4 Product Dependencies 17.4.
AT32UC3A 17.5 Functional Description 17.5.1 External Interrupts To enable an external interrupt EXTINTn must be written to 1 in register EN. Similarly, writing EXTINTn to 1 in register DIS disables the interrupt. The status of each Interrupt line can be observed in the CTRL register. Each external interrupt pin EXTINTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers.
AT32UC3A The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode. Still, as for the other external interrupts, the actual NMI input line can be enabled and disabled by accessing the registers in the External Interrupt Module. These interrupts are not enabled by default, allowing the proper interrupt vectors to be set up by the CPU before the interrupts are enabled. 17.5.3 Keypad scan support The External Interrupt Module also includes support for keypad scanning.
AT32UC3A 17.
AT32UC3A 17.6.
AT32UC3A 17.6.
AT32UC3A 17.6.3 External Interrupt Test Name: TEST Access Type: Read/Write 31 30 29 28 27 26 25 24 TEST_EN - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - NMI 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 • NMI If TEST_EN is 1, the value of this bit will be the value to the interrupt detector and the value on the pad will be ignored.
AT32UC3A 17.6.
AT32UC3A 17.6.
AT32UC3A 18. Flash Controller (FLASHC) Rev: 2.0.0.2 18.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle. • 32-bit HSB interface for reads from flash array and writes to page buffer. • 32-bit PB interface for issuing commands to and configuration of the controller.
AT32UC3A 18.4 Functional description 18.4.1 Bus interfaces The FLASHC has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control to and reading status from the controller. 18.4.2 Memory organization To maximize performance for high clock-frequency systems, FLASHC interfaces to a flash block with two read ports.
AT32UC3A The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in Figure 18-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. Table 18-1. User row addresses Memory type Start address, byte sized Size Main array 0 pw words = 4pw bytes User 2^23 = 8388608 128 words = 512 bytes Figure 18-1.
AT32UC3A The page buffer is also used for writes to the User page. Write operations can be prevented by programming the Memory Protection Unit of the CPU. Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption. Page buffer write operations are performed with 4 wait states.
AT32UC3A letting the CPU enter sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will result in an access pattern with IDLE HSB cycles. All the commands are protected by the same keyword, which has to be written in the eight highest bits of the FCMD register. Writing FCMD with data that does not contain the correct key and/or with an invalid command has no effect on the flash memory; however, the PROGE flag is set in the Flash Status Register (FSR).
AT32UC3A • Lock Error: The page to be programmed belongs to a locked region. A command must be executed to unlock the corresponding region before programming can start. 18.5.2 Erase All operation The entire memory is erased if the Erase All command (EA) is written to the Flash Command Register (FCMD). Erase All erases all bits in the flash array. The User page is not erased. All flash memory locations, the general-purpose fuse bits, and the security bit are erased (reset to 0xFF) after an Erase All.
AT32UC3A through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 18-2. General-purpose fuses with special functions GeneralPurpose fuse number Name Usage 15:0 LOCK Region lock bits. EPFL External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared.
AT32UC3A commands, together with the number of the fuse to write/erase, performs the desired operation. An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the security bit.
AT32UC3A 18.8 User interface 18.8.1 Address map The following addresses are used by the FLASHC. All offsets are relative to the base address allocated to the flash controller. Table 18-4.
AT32UC3A 18.8.2 Flash Control Register (FCR) Offset: 0x0 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - SASD 7 6 5 4 3 2 1 0 - FWS - - PROGE LOCKE - FRDY FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt. LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt.
AT32UC3A 18.8.3 Flash Command Register (FCMD) Offset: 0x4 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to be set. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY 23 22 21 20 PAGEN [15:8] 15 14 13 12 PAGEN [7:0] 7 6 - - 5 4 CMD CMD: Command This field defines the flash command.
AT32UC3A PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field is automatically updated every time the page buffer is written to. For every page buffer write, the PAGEN field is updated with the page number of the address being written to. Hardware automatically masks writes to the PAGEN field so that only bits representing valid page numbers can be written, all other bits in PAGEN are always 0.
AT32UC3A 18.8.4 Flash Status Register (FSR) Offset: 0x08 31 30 29 28 27 26 25 24 LOCK15 LOCK14 LOCK13 LOCK12 LOCK11 LOCK10 LOCK9 LOCK8 23 22 21 20 19 18 17 16 LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0 15 14 13 12 11 10 9 8 - - - - FSZ 7 6 5 4 3 2 1 0 - - QPRR SECURITY PROGE LOCKE - FRDY FRDY: Flash Ready Status 0: The flash controller is busy and the application must wait before running a new command.
AT32UC3A FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 18-7. Flash size FSZ Flash Size 0 32 KByte 1 64 kByte 2 128 kByte 3 256 kByte 4 384 kByte 5 512 kByte 6 768 kByte 7 1024 kByte LOCKx: Lock Region x Lock Status 0: The corresponding lock region is not locked. 1: The corresponding lock region is locked.
AT32UC3A 18.8.5 Flash General Purpose Fuse Register High (FGPFRHI) Offset: 0x0C 31 30 29 28 27 26 25 24 GPF63 GPF62 GPF61 GPF60 GPF59 GPF58 GPF57 GPF56 23 22 21 20 19 18 17 16 GPF55 GPF54 GPF53 GPF52 GPF51 GPF50 GPF49 GPF48 15 14 13 12 11 10 9 8 GPF47 GPF46 GPF45 GPF44 GPF43 GPF42 GPF41 GPF40 7 6 5 4 3 2 1 0 GPF39 GPF38 GPF37 GPF36 GPF35 GPF34 GPF33 GPF32 This register is only used in systems with more than 32 GP fuses.
AT32UC3A 18.8.6 Flash General Purpose Fuse Register Low (FGPFRLO) Offset: 0x10 31 30 29 28 27 26 25 24 GPF31 GPF30 GPF29 GPF28 GPF27 GPF26 GPF25 GPF24 23 22 21 20 19 18 17 16 GPF23 GPF22 GPF21 GPF20 GPF19 GPF18 GPF17 GPF16 15 14 13 12 11 10 9 8 GPF15 GPF14 GPF13 GPF12 GPF11 GPF10 GPF09 GPF08 7 6 5 4 3 2 1 0 GPF07 GPF06 GPF05 GPF04 GPF03 GPF02 GPF01 GPF00 GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state.
AT32UC3A 131 32058K AVR32-01/12
AT32UC3A 19. HSB Bus Matrix (HMATRIX) Rev: 2.3.0.1 19.1 Features • • • • • • • • • • • 19.
AT32UC3A 19.4.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode. 19.4.2 Last Access Master At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. 19.4.3 Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to its fixed default master.
AT32UC3A 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See Section “19.5.1.2” on page 134. 19.5.1.1 Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer.
AT32UC3A 19.5.2.2 Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave.
AT32UC3A 19.7 User Interface Table 19-1.
AT32UC3A Table 19-1.
AT32UC3A Table 19-1.
AT32UC3A 19.7.1 Bus Matrix Master Configuration Registers Register Name: MCFG0...MCFG15 Access Type: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
AT32UC3A 19.7.2 Bus Matrix Slave Configuration Registers Register Name: SCFG0...SCFG15 Access Type: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – ARBT 23 22 21 20 19 18 17 16 – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
AT32UC3A 19.7.3 Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write 31 30 29 28 27 26 M7PR 23 22 21 20 19 18 M5PR 15 14 13 6 17 16 12 11 10 9 8 1 0 M2PR 5 M1PR 24 M4PR M3PR 7 25 M6PR 4 3 2 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
AT32UC3A 19.7.4 Bus Matrix Priority Registers B For Slaves Register Name: PRBS0...PRBS15 Access Type: Read/Write 31 30 29 28 27 26 M15PR 23 22 21 20 19 18 M13PR 15 14 13 6 17 16 12 11 10 9 8 1 0 M10PR 5 M9PR 24 M12PR M11PR 7 25 M14PR 4 3 2 M8PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
AT32UC3A 19.7.
AT32UC3A 19.7.6 Bus Matrix Special Function Registers Register Name: SFR0...SFR15 Access Type: Read/Write Reset: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR • SFR: Special Function Register Fields The bitfields of these registers are described in the Peripherals chapter.
AT32UC3A 20. External Bus Interface (EBI) Rev: 1.0.0.1 20.
AT32UC3A 20.3 Block Diagram 20.3.1 External Bus Interface Figure 20-1 shows the organization of the External Bus Interface. Figure 20-1.
AT32UC3A 20.4 I/O Lines Description Table 20-1.
AT32UC3A Table 20-2. EBI Pins and Memory Controllers I/O Lines Connections EBI Pins 20.5 SDRAMC I/O Lines SMC I/O Lines A[22:15] Not Supported SMC_A[22:15] A[23] Not Supported SMC_A[23] D[15:0] D[15:0] D[15:0] Application Example 20.5.1 Hardware Interface Table 20-3 on page 148 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 20-3.
AT32UC3A Table 20-4.
AT32UC3A 20.5.2 Connection Examples Figure 20-2 shows an example of connections between the EBI and external devices. Figure 20-2.
AT32UC3A 20.6 Product Dependencies 20.6.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the GPIO lines. The programmer must first program the GPIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the GPIO Controller. 20.6.
AT32UC3A 20.7.3 Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller Section. 20.7.4 SDRAM Controller For information on the SDRAM Controller, refer to the SDRAM Section.
AT32UC3A 21. Peripheral DMA Controller (PDCA) rev: 1.0.0.0 21.1 Features 21.2 Overview • Generates Transfers to/from Peripherals such as USART, SSC and SPI • Two address pointers/counters per channel allowing double buffering The Peripheral DMA controller (PDCA) transfers data between on-chip peripheral modules such as USART, SPI, SSC and on- and off-chip memories. Using the PDCA avoids CPU intervention for data transfers, improving the performance of the microcontroller.
AT32UC3A 21.3 Block Diagram Peripheral 0 HSB to PB Bridge Peripheral Bus HSB Bus Matrix HSB Peripheral 1 Peripheral 2 Peripheral DMA Controller (PDCA) Interrupt Controller IRQ Peripheral (n-1) Handshake interfaces 21.4 Functional Description 21.4.1 Configuration Each channel in the PDCA has a set of configuration registers. Among these are the Memory Address Register (MAR), the Peripheral Select Register (PSR) and the Transfer Counter Register (TCR).
AT32UC3A transfer. The address will be increased by either 1, 2 or 4 depending on the size of the DMA transfer (Byte, Half-Word or Word). The Memory Address Register can be read at any time during transfer. 21.4.3 Transfer Counter Each channel has a 16-bit Transfer Counter Register (TCR). This register must be programmed with the number of transferred to be performed. TCR should contain the number of data items to be transferred independently of the transfer size.
AT32UC3A 21.4.9 Priority If more then one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel 0 the highest priority. 21.4.10 Error Handling If the memory address is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer.
AT32UC3A Offset Register Register Name Access Reset 0x24 Interrupt Disable Register IDR Write-only - 0x28 Interrupt Mask Register IMR Read-only 0x00000000 0x2C Interrupt Status Register ISR Read-only 0x00000000 157 32058K AVR32-01/12
AT32UC3A 21.5.3 Name: PDCA Memory Address Register MAR Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MADDR 23 22 21 20 MADDR 15 14 13 12 MADDR 7 6 5 4 MADDR • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA. During transfer, MADDR will point to the next memory location to be read/written.
AT32UC3A 21.5.4 Name: PDCA Peripheral Select Register PSR Access Type: Read/Write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PID • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel.
AT32UC3A 21.5.5PDCA Transfer Counter Register Name: TCR Access Type: Read/Write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCV 7 6 5 4 TCV • TCV: Transfer Counter Value Number of data items to be transferred by PDCA. TCV must be programmed with the total number of transfers to be made. During transfer, TCV contains the number of remaining transfers to be done.
AT32UC3A 21.5.6 Name: PDCA Memory Address Reload Register MARR Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MARV 23 22 21 20 MARV 15 14 13 12 MARV 7 6 5 4 MARV • MARV: Memory Address Reload Value Reload Value for the Memory Address Register (MAR). This value will be loaded into MAR when TCR reaches zero if the TCRR has a non-zero value.
AT32UC3A 21.5.7 Name: PDCA Transfer Counter Reload Register TCRR Access Type: Read/Write 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCRV 7 6 5 4 TCRV • TCRV: Transfer Counter Reload Value Reload value for the Transfer Counter Register (TCR). When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value.
AT32UC3A 21.5.8 Name: PDCA Control Register CR Access Type: Write-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ECLR 7 6 5 4 3 2 1 0 - - - - - - TDIS TEN • ECLR: Error Clear 0 = No Effect. 1 = Clear Transfer Error (TERR) flag in the Status Register (SR). Clearing the Transfer Error flag will allow the channel to transmit data.
AT32UC3A 21.5.
AT32UC3A 21.5.10 Name: PDCA Status Register SR Access Type: Read 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TEN • TEN: Transfer Enabled 0 = Transfer is disabled for the DMA channel 1 = Transfer is enabled for the DMA channel.
AT32UC3A 21.5.11 Name: PDCA Interrupt Enable Register IER Write-only Access Type: 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error 0 = No effect. 1 = Enable Transfer Error interrupt. • TRC: Transfer Complete 0 = No effect. 1 = Enable Transfer Complete interrupt. • RCZ: Reload Counter Zero 0 = No effect.
AT32UC3A 21.5.12 Name: PDCA Interrupt Disable Register IDR Write-only Access Type: 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error 0 = No effect. 1 = Disable Transfer Error interrupt. • TRC: Transfer Complete 0 = No effect. 1 = Disable Transfer Complete interrupt. • RCZ: Reload Counter Zero 0 = No effect.
AT32UC3A 21.5.13 Name: PDCA Interrupt Mask Register IMR Read-only Access Type: 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error 0 = Transfer Error interrupt is disabled. 1 = Transfer Error interrupt is enabled. • TRC: Transfer Complete 0 = Transfer Complete interrupt is disabled.
AT32UC3A 21.5.14 Name: PDCA Interrupt Status Register ISR Read-only Access Type: 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error 0 = No transfer errors have occurred. 1 = A transfer error has occurred.
AT32UC3A 22. General-Purpose Input/Output Controller (GPIO) Rev. 1.1.0.2 22.1 Features Each I/O line of the GPIO features: • • • • • • 22.2 Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line. A glitch filter providing rejection of pulses shorter than one clock cycle. Open Drain mode enabling sharing of an I/O line between the MCU and external components. Input visibility and output control. Multiplexing of up to four peripheral functions per I/O line.
AT32UC3A • • • • 22.3.2 Number of I/O pins. Functions implemented on each pin. Peripheral function(s) multiplexed on each I/O pin. Reset state of registers. Interrupt Lines The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO interrupt requires the interrupt controller to be programmed first. 22.3.3 22.4 Power and Clock Management The clock for the GPIO is controlled by the power manager.
AT32UC3A 22.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or more peripheral functions, the selection is controlled with the register GPER. If a bit in the register is set, the corresponding pin is controlled by the GPIO. If a bit is cleared, the corresponding pin is controlled by a peripheral function. 22.4.3 Peripheral Selection The GPIO provides multiplexing of up to four peripheral functions on a single pin.
AT32UC3A Figure 22-2. Output line timings clock Write GPIO_OVR to 1 Write GPIO_OVR to 0 PBA Access PBA Access GPIO_OVR / I/O Line GPIO_PVR 22.4.7 Interrupts The GPIO can be programmed to generate an interrupt when it detects an input change on an I/O line. The module can be configured to signal an interrupt whenever a pin changes value or only to trigger on rising edges or falling edges. Interrupt is enabled on a pin by setting the corresponding bit in IER (Interrupt Enable Register).
AT32UC3A Figure 22-3. Interrupt timing with glitch filter disabled clock Pin Level GPIO_IFR The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In the example, the first pulse is rejected while the second pulse is accepted and causes an interrupt request. Figure 22-4.
AT32UC3A 22.5 General Purpose Input/Output (GPIO) User Interface The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32bit ports that are configurable through an PB interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports is product specific.
AT32UC3A GPIO Register Map Table 22-2.
AT32UC3A GPIO Register Map Table 22-2.
AT32UC3A 22.5.2 Name: GPIO Enable Register GPER Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: GPIO Enable 0 = A peripheral function controls the corresponding pin. 1 = The GPIO controls the corresponding pin.
AT32UC3A 22.5.3 Name: Peripheral Mux Register 0 PMR0 Read, Write, Set, Clear, Toggle Access: 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Peripheral Multiplexer Select bit 0 22.5.
AT32UC3A 22.5.5 Name: Output Driver Enable Register ODER Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Driver Enable 0 = The output driver is disabled for the corresponding pin.
AT32UC3A 22.5.6 Name: Output Value Register OVR Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0 = The value to be driven on the I/O line is 0. 1 = The value to be driven on the I/O line is 1.
AT32UC3A 22.5.7 Name: Pin Value Register PVR Access: Read 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0 = The I/O line is at level ‘0’. 1 = The I/O line is at level ‘1’.
AT32UC3A 22.5.8 Name: Pull-up Enable Register PUER Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pull-up Enable 0 = The internal pull-up resistor is disabled for the corresponding pin.
AT32UC3A 22.5.9 Name: Open Drain Mode Enable Register ODMER Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Open Drain Mode Enable 0 = Open drain mode is disabled for the corresponding pin.
AT32UC3A 22.5.10 Name: Interrupt Enable Register IER Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0 = Interrupt is disabled for the corresponding pin. 1 = Interrupt is enabled for the corresponding pin.
AT32UC3A 22.5.11 Name: Interrupt Mode Register 0 IMR0 Read, Write, Set, Clear, Toggle Access: 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Mode Bit 0 22.5.
AT32UC3A 22.5.13 Name: Glitch Filter Enable Register GFER Access: Read, Write, Set, Clear, Toggle 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Glitch Filter Enable 0 = Glitch filter is disabled for the corresponding pin. 1 = Glitch filter is enabled for the corresponding pin.
AT32UC3A 22.5.14 Name: Interrupt Flag Register IFR Access: Read, Clear 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 0 = An interrupt condition has been detected on the corresponding pin. 1 = No interrupt condition has been detected on the corresponding pin.
AT32UC3A 22.6 Programming Examples 22.6.1 8-bit LED-Chaser // Set R0 to GPIO base address mov R0, LO(AVR32_GPIO_BASE_ADDRESS) orh R0, HI(AVR32_GPIO_BASE_ADDRESS) // Enable GPIO control of pin 0-8 mov R1, 0xFF st.w R0[AVR32_GPIO_GPERS], R1 // Set initial value of port mov R2, 0x01 st.w R0[AVR32_GPIO_OVRS], R2 // Set up toggle value. Two pins are toggled // in each round. The bit that is currently set, // and the next bit to be set.
AT32UC3A mov R1, 0x0000 orh R1, 0x0003 st.w R0[AVR32_GPIO_ODERC], R1 // Make the GPIO control the pins st.w R0[AVR32_GPIO_GPERS], R1 // Select peripheral B on PC16-PC17 st.w R0[AVR32_GPIO_PMR0S], R1 st.w R0[GPIO_PMR1C], R1 // Enable peripheral control st.
AT32UC3A 23. Serial Peripheral Interface (SPI) Rev: 1.9.9.3 23.
AT32UC3A 23.3 Block Diagram Figure 23-1.
AT32UC3A 23.4 Application Block Diagram Figure 23-2.
AT32UC3A 23.5 Signal Description Table 23-1.
AT32UC3A 23.6 Product Dependencies 23.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. To use the local loopback function the SPI pins must be controlled by the SPI. 23.6.2 Power Management The SPI clock is generated by the Power Manager.
AT32UC3A 23.7 Functional Description 23.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
AT32UC3A Figure 23-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 23-4.
AT32UC3A 23.7.3 Master Mode Operations When configured in Master Mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate.
AT32UC3A 23.7.3.1 Master Mode Block Diagram Figure 23-5. Master Mode Block Diagram FDIV SPI_CSR0..3 SCBR MCK 0 Baud Rate Generator MCK/N SPCK 1 SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
AT32UC3A 23.7.3.2 Master Mode Flow Diagram Figure 23-6. Master Mode Flow Diagram S SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
AT32UC3A 23.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32, by a value between 1 and 255. The selection between Master Clock or Master Clock divided by 32 is done by the FDIV value set in the Mode Register This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255*32. Programming the SCBR field at 0 is forbidden.
AT32UC3A 23.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in MR (Mode Register).
AT32UC3A 23.7.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.
AT32UC3A 23.7.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open-drain through the PIO controller, so that external pull up resistors are needed to guarantee high level.
AT32UC3A Figure 23-9.
AT32UC3A 23.8 Serial Peripheral Interface (SPI) User Interface Table 23-3.
AT32UC3A 23.8.1 SPI Control Register Name: CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPDIS is set, SPI finishes its transfer.
AT32UC3A 23.8.2 SPI Mode Register Name: MR Access Type: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – – MODFDIS FDIV PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
AT32UC3A • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
AT32UC3A 23.8.3 SPI Receive Data Register Name: RDR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer.
AT32UC3A 23.8.4 SPI Transmit Data Register Name: TDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
AT32UC3A 23.8.
AT32UC3A 1 = Both TCR and TNCR has a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in TDR. 1 = TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled.
AT32UC3A 23.8.
AT32UC3A 23.8.
AT32UC3A 23.8.
AT32UC3A 23.8.9 SPI Chip Select Register Name: CSR0... CSR3 Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT CSNAAT NCPHA CPOL • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
AT32UC3A . Table 23-4. BITS, Bits Per Transfer BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field.
AT32UC3A Otherwise, the following equations determine the delay: If FDIV is 0: DLYBS Delay Before SPCK = ------------------MCK If FDIV is 1: N × DLYBS Delay Before SPCK = ----------------------------MCK Note: N = 32 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
AT32UC3A 24. Two-Wire Interface (TWI) 2.1.1.0 24.
AT32UC3A 24.3 List of Abbreviations Table 24-2. 24.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 24-1.
AT32UC3A 24.5 Application Block Diagram Figure 24-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 24.6 I/O Lines Description Table 24-3. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 24.7 24.7.
AT32UC3A 24.7.3 Interrupt The TWI interface has an interrupt line connected to the Interrupt Controller (INTC). In order to handle interrupts, the INTC must be programmed before configuring the TWI. 24.8 24.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 24-4).
AT32UC3A 24.10 Master Mode 24.10.1 Definition The Master is the device which starts a transfer, generates a clock and stops it. 24.10.2 Application Block Diagram Figure 24-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 24.10.
AT32UC3A Figure 24-6. Master Write with One Data Byte S TWD DADR W A DATA A P TXCOMP TXRDY STOP sent automaticaly (ACK received and TXRDY = 1) Write THR (DATA) Figure 24-7. Master Write with Multiple Data Byte S TWD DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Figure 24-8.
AT32UC3A RXRDY bit is set in the status register, a character has been received in the receive-holding register (RHR). The RXRDY bit is reset when reading the RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 24-9. When a multiple data byte read is performed, with or without IADR, the STOP bit must be set after the next-to-last data received. See Figure 24-10.
AT32UC3A If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0. n the figures below the following abbreviations are used:I •S Start • Sr Repeated Start •P Stop •W Write •R Read •A Acknowledge •N Not Acknowledge • DADR Device Address • IADR Internal Address Figure 24-11.
AT32UC3A 24.10.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device: (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
AT32UC3A 24.11.3 Read-write Flowcharts The following flowcharts shown in Figure 24-13 to Figure 24-18 on page 234 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (IER) be configured first. Figure 24-13. TWI Write Operation with Single Data Byte without Internal Address.
AT32UC3A Figure 24-14.
AT32UC3A Figure 24-15.
AT32UC3A Figure 24-16.
AT32UC3A Figure 24-17.
AT32UC3A Figure 24-18.
AT32UC3A 24.12 Multi-master Mode 24.12.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
AT32UC3A 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 24-19.
AT32UC3A Figure 24-21.
AT32UC3A 24.13 Slave Mode 24.13.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 24.13.2 Application Block Diagram Figure 24-22. Slave Mode Typical Application Block Diagram VDD R Master TWD Host with TWI Interface 24.13.
AT32UC3A As soon as data is written in the THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Note that a STOP or a repeated START always follows a NACK. See Figure 24-23 on page 240. 24.13.4.
AT32UC3A As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode. 24.13.5 Data Transfer 24.13.5.1 Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
AT32UC3A Figure 24-24. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK S TWD ADR W NA DATA NA SADR matches, TWI answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSVACC Notes: 24.13.5.3 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2.
AT32UC3A 24.13.6 Clock Synchronization In both read and write modes, it may happen that THR/RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. 24.13.6.1 Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
AT32UC3A 24.13.6.2 Clock Synchronization in Write Mode The clock is tied low if the shift register and the RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until RHR is read. Figure 24-27 on page 243 describes the clock synchronization in Read mode. Figure 24-27.
AT32UC3A 24.13.7 Reversal after a Repeated Start 24.13.7.1 Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 24-28 on page 244 describes the repeated start + reversal from Read to Write mode. Figure 24-28.
AT32UC3A 24.13.8 Read Write Flowcharts The flowchart shown in Figure 24-30 on page 245 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (IER) be configured first. Figure 24-30.
AT32UC3A 24.14 Two-wire Interface (TWI) User Interface 24.14.1 Register Mapping Table 24-4.
AT32UC3A This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (THR). • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. - In single data byte master read, the START and STOP must both be set.
AT32UC3A 24.14.
AT32UC3A 24.14.4 TWI Slave Mode Register Name: SMR Access: Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call.
AT32UC3A 24.14.5 TWI Internal Address Register Name: IADR Access: Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
AT32UC3A 24.14.6 TWI Clock Waveform Generator Register Name: CWGR Access: Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV CWGR is only used in Master mode.
AT32UC3A 24.14.7 TWI Status Register Name: SR Access: Read-only Reset Value: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
AT32UC3A TXRDY used in Slave mode: 0 = As soon as data is written in the THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill THR to avoid losing it.
AT32UC3A NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0 = Arbitration won.
AT32UC3A 1 = Both TCR and TNCR have a value of 0. 24.14.
AT32UC3A 1 = Enables the corresponding interrupt. 24.14.
AT32UC3A 24.14.
AT32UC3A Access: Read-only Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Master or Slave Receive Holding Data 24.14.
AT32UC3A 25. Synchronous Serial Controller (SSC) Rev: 3.0.0.2 25.
AT32UC3A 25.3 Block Diagram Figure 25-1. Block Diagram High Speed Bus Peripheral Bus Bridge PDCA Peripheral Bus TX_FRAME_SYNC TX_CLOCK TX_DATA Power CLK_SSC Manager PIO SSC Interface RX_FRAME_SYNC RX_CLOCK Interrupt Control RX_DATA SSC Interrupt 25.4 Application Block Diagram Figure 25-2.
AT32UC3A 25.5 I/O Lines Description Table 25-1. I/O Lines Description Pin Name Pin Description RX_FRAME_SYNC Receiver Frame Synchro Input/Output RX_CLOCK Receiver Clock Input/Output RX_DATA Receiver Data Input TX_FRAME_SYNC Transmitter Frame Synchro Input/Output TX_CLOCK Transmitter Clock Input/Output TX_DATA Transmitter Data Output 25.6 25.6.1 Type Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
AT32UC3A Figure 25-3.
AT32UC3A 25.7.1.1 Clock Divider Figure 25-4. Divided Clock Block Diagram Clock Divider CMR CLK_SSC /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive.
AT32UC3A The transmitter can also drive the TX_CLOCK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TX_CLOCK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 25-6.
AT32UC3A Figure 25-7. Receiver Clock Management RX_CLOCK (pin) Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS 25.7.1.4 INV MUX Tri-state Controller CKI CKG Receiver Clock Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers.
AT32UC3A Figure 25-8. Transmitter Block Diagram CR.TXEN SR.TXEN CR.TXDIS TFMR.DATDEF 1 TX_FRAME_SYNC RX_FRAME_SYNC Transmitter Clock Start Selector TX_DATA 0 TFMR.MSBF Transmit Shift Register 0 TFMR.FSDEN TCMR.STTDLY TFMR.DATLEN 25.7.3 TCMR.STTDLY TFMR.FSDEN TFMR.DATNB THR 1 TSHR TFMR.FSLEN Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission.
AT32UC3A Figure 25-9. Receiver Block Diagram R X _ C L O C K (p in ) T ri-sta te C o n tro lle r MUX C lo ck O u tp u t T ra n sm itte r C lo ck D ivid e r C lo ck D a ta Tra n sfe r CKO CKS 25.7.4 IN V MUX T ri-sta te C o n tro lle r CKI CKG R e ce ive r C lo ck Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of TCMR and in the Receive Start Selection (START) field of RCMR.
AT32UC3A Figure 25-10.
AT32UC3A 25.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TX_FRAME_SYNC and RX_FRAME_SYNC, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (RFMR) and in the Transmit Frame Mode Register (TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported.
AT32UC3A 25.7.6 Receive Compare Modes Figure 25-12. Receive Compare Modes RX_CLOCK RX_DATA (Input) CMP0 CMP1 CMP2 CMP3 Ignored B0 B1 B2 Start FSLEN Up to 16 Bits (4 in This Example) 25.7.6.1 25.7.7 STTDLY DATLEN Compare Functions Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the Compare 0 Register (RC0R).
AT32UC3A Data Frame Registers Table 25-3. Transmitter Receiver Field Length Comment TFMR RFMR DATLEN Up to 32 Size of word TFMR RFMR DATNB Up to 16 Number of words transmitted in frame TFMR RFMR MSBF TFMR RFMR FSLEN Up to 16 Size of Synchro data register TFMR DATDEF 0 or 1 Data default value ended TFMR FSDEN Most significant bit first Enable send TSHR TCMR RCMR PERIOD Up to 512 Frame size TCMR RCMR STTDLY Up to 255 Size of transmit start delay Figure 25-13.
AT32UC3A Figure 25-14. Transmit Frame Format in Continuous Mode Start TX_DATA Data Data From THR From THR Default DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the THR Note: 1. STTDLY is set to 0. In this example, THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 25-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RX_DATA Note: 25.7.8 Data Data To RHR To RHR DATLEN DATLEN 1.
AT32UC3A Figure 25-16. Interrupt Block Diagram IMR PDCA IER IDR Set Clear TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control RXBUFF ENDRX SSC Interrupt Receiver RXRDY OVRUN RXSYNC 25.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 25-17.
AT32UC3A Figure 25-18. Codec Application Block Diagram TX_CLOCK TX_FRAME_SYNC SSC Frame sync (FSYNC) CODEC Serial Data Out TX_DATA Serial Data In RX_DATA RX_FRAME_SYNC RX_CLOCK Serial Data Clock (SCLK) Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 25-19.
AT32UC3A 25.9 User Interface Table 25-4.
AT32UC3A 25.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in CR. • TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit.
AT32UC3A 25.9.2 Name: Clock Mode Register CMR Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is CLK_SSC/2.
AT32UC3A 25.9.3 Name: Receive Clock Mode Register RCMR Access Type: Read/Write Offset: 0x10 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated.
AT32UC3A • CKG: Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RX_FRAME_SYNC Low 0x2 Receive Clock enabled only if RX_FRAME_SYNC High 0x3 Reserved • CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge.
AT32UC3A 25.9.4 Name: Receive Frame Mode Register RFMR Access Type: Read/Write Offset: 0x14 Reset value: 0x00000000 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLENHI 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • FSLENHI: Receive Frame Sync Length High part The four MSB of the FSLEN bitfield.
AT32UC3A This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. • LOOP: Loop Mode 0: Normal operating mode. 1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK.
AT32UC3A 25.9.5 Name: Transmit Clock Mode Register TCMR Access Type: Read/Write Offset: 0x18 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated.
AT32UC3A • CKG: Transmit Clock Gating Selection CKG Transmit Clock Gating 0x0 None, continuous clock 0x1 Transmit Clock enabled only if TX_FRAME_SYNC Low 0x2 Transmit Clock enabled only if TX_FRAME_SYNC High 0x3 Reserved • CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge.
AT32UC3A 25.9.6 Name: Transmit Frame Mode Register TFMR Access Type: Read/Write Offset: 0x1C Reset value: 0x00000000 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLENHI 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • FSLENHI: Transmit Frame Sync Length High part The four MSB of the FSLEN bitfield.
AT32UC3A Pulse length is equal to ({FSLENHI,FSLEN} + 1) Transmit Clock periods, i.e., the pulse length can range from 1 to 16 Transmit Clock periods. If {FSLENHI,FSLEN} is 0, the Transmit Frame Sync signal is generated during one Transmit Clock period. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
AT32UC3A 25.9.7 Name: SSC Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in RFMR.
AT32UC3A 25.9.8 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in TFMR.
AT32UC3A 25.9.
AT32UC3A 25.9.
AT32UC3A 25.9.
AT32UC3A 25.9.
AT32UC3A 25.9.13 Name: Status Register SR Access Type: Read-only Offset: 0x40 Reset value: 0x000000CC 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled. • TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled.
AT32UC3A 1: End of PDCA transfer when Receive Counter Register has arrived at zero. • OVRUN: Receive Overrun 0: No data has been loaded in RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in RHR while previous data has not yet been read since the last read of the Status Register. • RXRDY: Receive Ready 0: RHR is empty. 1: Data has been received and loaded in RHR. • TXBUFE: Transmit Buffer Empty 0: TCR or TNCR have a value other than 0.
AT32UC3A 25.9.14 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x44 Reset value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt.
AT32UC3A 1: Enables the Receive Ready Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Buffer Empty Interrupt • ENDTX: End of Transmission Interrupt Enable 0: No effect. 1: Enables the End of Transmission Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt.
AT32UC3A 25.9.15 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x48 Reset value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt.
AT32UC3A 1: Disables the Receive Ready Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Buffer Empty Interrupt. • ENDTX: End of Transmission Interrupt Disable 0: No effect. 1: Disables the End of Transmission Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt.
AT32UC3A 25.9.16 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x4C Reset value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.
AT32UC3A 26. Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Rev. 4.0.0.2 26.1 Features • Programmable Baud Rate Generator • 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications • • • • • • 26.2 – 1, 1.
AT32UC3A 26.3 Block Diagram Figure 26-1.
AT32UC3A 26.4 Application Block Diagram Figure 26-2.
AT32UC3A 26.5 I/O Lines Description Table 26-1.
AT32UC3A 26.6 Product Dependencies 26.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
AT32UC3A 26.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: •5- to 9-bit full-duplex asynchronous serial communication –MSB- or LSB-first –1, 1.
AT32UC3A 26.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
AT32UC3A This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the highest possible clock and that OVER is programmed at 1. 26.7.1.2 Baud Rate Calculation Example Table 26-2 on page 306 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 26-2. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.
AT32UC3A 26.7.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
AT32UC3A has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the CLK pin. If the internal clock CLK_USART is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the CLK pin, even if the value programmed in CD is odd. 26.7.1.
AT32UC3A Generator Register (BRGR). The resulting clock can be provided to the CLK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode.
AT32UC3A 26.7.3 26.7.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR).
AT32UC3A 26.7.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time.
AT32UC3A Figure 26-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the MR register.
AT32UC3A Figure 26-10. Start Frame Delimiter Preamble Length is set to 0 Manchester encoded data Manchester encoded data Manchester encoded data SFD DATA Txd SFD One bit start frame delimiter DATA Txd Command Sync start frame delimiter SFD DATA Txd Data Sync start frame delimiter 26.7.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift.
AT32UC3A The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0.
AT32UC3A 26.7.3.5 Manchester Decoder When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble sequence.
AT32UC3A Figure 26-15. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Manchester encoded data Preamble Mismatch invalid pattern SFD Txd DATA Preamble Length is set to 8 Figure 26-16.
AT32UC3A Figure 26-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod control Fdown frequency Carrier Serial Configuration Interface bi-dir line ASK/FSK downstream transmitter Downstream Receiver Manchester decoder USART Receiver Manchester encoder USART Emitter PA RF filter Mod VCO control The USART module is configured as a Manchester encoder/decoder.
AT32UC3A Figure 26-19. FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 26.7.4 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit.
AT32UC3A Figure 26-21.
AT32UC3A 26.7.4.2 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (MR). The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 321. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
AT32UC3A Figure 26-22. Parity Error Baud Rate Clock RXD Start D0 Bit Write US_CR D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 PARE RXRDY 26.7.4.3 Multidrop Mode If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
AT32UC3A Figure 26-23. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 26-7 on page 322 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 26-7. 26.7.4.
AT32UC3A handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
AT32UC3A 26.7.4.6 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1.
AT32UC3A After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations.
AT32UC3A Setting the USART to operate with hardware handshaking is performed by writing the MODE field in the Mode Register (MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception.
AT32UC3A As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 26-30. Connection of a Smart Card to the USART USART CLK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed.
AT32UC3A Figure 26-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D2 D1 D4 D3 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 26-32. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 26.7.5.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (NER) register.
AT32UC3A MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 26.7.5.7 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (CSR). 26.7.
AT32UC3A Table 26-9. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Figure 26-34 on page 330 shows an example of character transmission. Figure 26-34. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 1 0 1 0 1 0 1 0 1 TXD 3 16 Bit Period Bit Period 26.7.6.2 IrDA Baud Rate Table 26-10 on page 330 gives some examples of CD values, baud rate error and pulse duration.
AT32UC3A Table 26-10. IrDA Baud Rate Error (Continued) Peripheral Clock 26.7.6.3 Baud Rate CD Baud Rate Error Pulse Time 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.
AT32UC3A 26.7.7 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 26-36 on page 332. Figure 26-36.
AT32UC3A 26.7.8 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
AT32UC3A 26.7.8.2 Baud Rate In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See Section “26.7.1.4” on page 307. However, there are some restrictions: In SPI Master Mode: • the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK pin.
AT32UC3A Figure 26-38. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) 2 1 4 3 5 7 6 8 CLK (CPOL= 0) CLK (CPOL= 1) MOSI SPI Master ->TXD SPI Slave ->RXD MISO SPI Master ->RXD SPI Slave ->TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master ->RTS SPI Slave ->CTS Figure 26-39.
AT32UC3A 26.7.8.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed.
AT32UC3A 26.7.9 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 26.7.9.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 26-40. Normal Mode Configuration RXD Receiver TXD Transmitter 26.7.9.
AT32UC3A 26.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 26-43 on page 338. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 26-43.
AT32UC3A 26.8 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) User Interface 26.8.1 Register Mapping Table 26-12.
AT32UC3A 26.8.2 USART Control Register Name: CR Access Type: Write-only Offset: 0x0 Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select – If USART does not operate in SPI Master Mode (MODE … 0xE): 0: No effect.
AT32UC3A • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in CSR. • STPBRK: Stop Break 0: No effect.
AT32UC3A 1: Resets the transmitter. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
AT32UC3A 26.8.3 USART Mode Register Name: MR Access Type: Read-write Offset: 0x4 Reset Value: - 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 15 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 CHMODE 7 NBSTOP 6 CHRL 5 USCLKS MODE • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit.
AT32UC3A 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • CLKO: Clock Output Select 0: The USART does not drive the CLK pin.
AT32UC3A 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved • PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase – If USART does not operate in SPI Mode (MODE is … 0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode.
AT32UC3A • MODE MODE Mode of the USART 0 0 0 0 Normal 0 0 0 1 RS485 0 0 1 0 Hardware Handshaking 0 1 0 0 IS07816 Protocol: T = 0 0 1 1 0 IS07816 Protocol: T = 1 1 0 0 0 IrDA 1 1 1 0 SPI Master 1 1 1 1 SPI Slave Others Reserved 346 32058K AVR32-01/12
AT32UC3A 26.8.
AT32UC3A 26.8.
AT32UC3A Access Type: Write-only Offset: 0xC Reset Value: - 31 – 30 – 29 28 27 26 25 24 MANEA 23 – 22 – 21 – 20 MANE 19 CTSIC 18 – 17 – 16 – 15 14 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • MANEA: Manchester Error Interrupt Disable • MANE: Manchester Error Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • RXBUFF: Buffer Full
AT32UC3A 26.8.
AT32UC3A 26.8.
AT32UC3A Access Type: Read-only Offset: 0x14 Reset Value: - 31 – 30 – 29 28 27 26 25 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 14 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA.
AT32UC3A – If USART operates in SPI Slave Mode (MODE = 0xF): UNRE = 0: No SPI underrun error has occurred since the last RSTSTA. UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled. TXEMPTY == 1: Means that the Transmit Shift Register is empty and that there is no data in THR.
AT32UC3A 1: At least one complete character has been received and RHR has not yet been read.
AT32UC3A 26.8.8 USART Receive Holding Register Name: RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. • RXCHR: Received Character Last character received if RXRDY is set.
AT32UC3A 26.8.9 USART Transmit Holding Register Name: THR Access Type: Write-only Offset: 0x1C Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command.
AT32UC3A 26.8.10 USART Baud Rate Generator Register Name: BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP– 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8.
AT32UC3A 26.8.11 USART Receiver Time-out Register Name: RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 – – – – – – – – TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
AT32UC3A 26.8.12 USART Transmitter Timeguard Register Name: TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
AT32UC3A 26.8.13 USART FI DI RATIO Register Name: FIDI Access Type: Read-write Offset: 0x40 Reset Value: 0x00000174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
AT32UC3A 26.8.14 USART Number of Errors Register Name: NER Access Type: Read-only Offset: 0x44 Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
AT32UC3A 26.8.15 USART IrDA FILTER Register Name: IFR Access Type: Read-write Offset: 0x4C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
AT32UC3A 26.8.16 USART Manchester Configuration Register Name: MAN Access Type: Read-write Offset: 0x50 Reset Value: 0x30011004 31 – 30 DRIFT 29 1 28 RX_MPOL 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 7 – 6 – 5 – 4 – 3 2 25 24 RX_PP 17 16 RX_PL 9 8 TX_PP 1 0 TX_PL • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.
AT32UC3A • TX_PP: Transmitter Preamble Pattern TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set) 0 0 ALL_ONE 0 1 ALL_ZERO 1 0 ZERO_ONE 1 1 ONE_ZERO • TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period 364 32058K AVR32-01/12
AT32UC3A 26.8.17 USART Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 VARIANT 16 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 VERSION 3 2 VERSION • VARIANT Reserved. No functionality associated. • VERSION Version of the module. No functionality associated.
AT32UC3A 27. Static Memory Controller (SMC) Rev. 1.0.0.0 27.1 Features • • • • • • • • • • • • 27.
AT32UC3A 27.3 Block Diagram Figure 27-1. Block Diagram NCS[5:0] Bus Matrix NRD SMC Chip Select NWR0/NWE A0/NBS0 SMC NWR1/NBS1 A1/NWR2/NBS2 PM CLK_SMC NWR3/NBS3 GPIO Controller NCS[5:0] NRD NWR0/NWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 A[25:2] D[31:0] NWAIT A[25:2] D[31:0] NWAIT User Interface Peripheral Bus 27.4 I/O Lines Description Table 27-1.
AT32UC3A 27.5 Product Dependencies 27.5.1 EBI I/O Lines The Static Memory Controller signals pass througth the EBI module where they are multiplexed. The programmer must first configure the GPIO controller to assign the EBI pins corresponding to SMC signals to their peripheral function. If I/O lines of the EBI corresponding to SMC signals are not used by the application, they can be used for other purposes by the GPIO Controller. 27.6 Functionnal Description 27.6.1 27.6.1.
AT32UC3A If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 27-3). A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory. Memory Connections for 6 External Devices Figure 27-3.
AT32UC3A Figure 27-4. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Figure 27-5. Memory Enable Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 27-6.
AT32UC3A – Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. • For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
AT32UC3A Figure 27-7. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] SMC A1 NWR0 A[23:1] A[0] Write Enable NWR1 NRD NCS[3] Read Enable Memory Enable D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable – Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed.
AT32UC3A Figure 27-8. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) D[15:0] D[15:0] D[31:16] A[25:2] A[23:0] NWE Write Enable NBS0 Low Byte Enable NBS1 High Byte Enable NBS2 SMC NBS3 Read Enable NRD Memory Enable NCS[3] D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable Table 27-2.
AT32UC3A 27.6.4.1 Read Waveforms The read cycle is shown on Figure 27-9. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 27-9.
AT32UC3A – NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. – Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e.
AT32UC3A Figure 27-10. No Setup, No Hold On NRD and NCS Read Signals CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] NRD_SETUP NCS_RD_PULSE NRD_CYCLE NRD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_PULSE NCS_RD_PULSE NRD_CYCLE – Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 27.6.4.
AT32UC3A Figure 27-11. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling – Read is Controlled by NCS (READ_MODE = 0) Figure 27-12 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised.
AT32UC3A Figure 27-12. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling 27.6.4.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 27-13. The write cycle starts with the address setting on the memory address bus. – NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1.
AT32UC3A Figure 27-13. Write Cycle CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NCS_WR_PULSE NWE_HOLD NCS_WR_HOLD NWE_CYCLE – Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
AT32UC3A Figure 27-14. Null Setup and Hold Values of NCS and NWE in Write Cycle CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE, NWE0, NWE1 NCS D[15:0] NWE_SETUP NCS_WR_SETUP NWE_CYCLE NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE – Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 27.6.4.
AT32UC3A Figure 27-15. WRITE_MODE = 1. The write operation is controlled by NWE CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] – Write is Controlled by NCS (WRITE_MODE = 0) Figure 27-16 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
AT32UC3A The SETUP register groups the definition of all setup parameters: • NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP The PULSE register groups the definition of all pulse parameters: • NRD_PULSE, ncs_rd_pULSE, nwe_pULSE, ncs_wr_pULSE The CYCLE register groups the definition of all cycle parameters: • NRD_CYCLE, NWE_CYCLEe Table 27-3 shows how the timing parameters are coded and their permitted range. Coding and Range of Timing Parameters Table 27-3.
AT32UC3A 27.6.5.1 Chip Select Wait States The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to 1. Figure 27-17 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
AT32UC3A Figure 27-17.
AT32UC3A 27.6.5.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
AT32UC3A Figure 27-19. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No Setup.
AT32UC3A Figure 27-20. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Internal write controlling signal external write controlling signal(NWE) No hold Read setup=1 NRD D[15:0] Write cycle (WRITE_MODE = 1) 27.6.5.3 Early Read Wait state Read cycle (READ_MODE=0 or READ_MODE=1) Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
AT32UC3A 27.6.5.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 27-17 on page 384. 27.6.6 Data Float Wait States Some memory devices are slow to release the external bus.
AT32UC3A Figure 27-21. TDF Period in NRD Controlled Read Access (TDF = 2) CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] tPACC TDF = 2 clock cycles NRD controlled read operation Figure 27-22.
AT32UC3A 27.6.6.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 27-23 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
AT32UC3A • read access followed by a write access on the same chip select, with no TDF optimization. Figure 27-24. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Read1 hold = 1 Read2 controlling signal(NRD) Read2 setup = 1 TDF_CYCLES = 6 D[15:0] 5 TDF WAIT STATES Read 2 cycle TDF_MODE=0 (optimization disabled) Read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 27-25.
AT32UC3A Figure 27-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Write2 setup = 1 Read1 hold = 1 Write2 controlling signal(NWE) TDF_CYCLES = 5 D[15:0] 4 TDF WAIT STATES Read1 cycle TDF_CYCLES = 5 27.6.7 Read to Write Wait State Write 2 cycle TDF_MODE=0 (optimization disabled) External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
AT32UC3A 27.6.7.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 2727.
AT32UC3A Figure 27-28. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10).
AT32UC3A 27.6.7.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 27-29 and Figure 27-30. After deassertion, the access is completed: the hold step of the access is performed.
AT32UC3A Figure 27-30. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11).
AT32UC3A 27.6.7.4 NWAIT Latency and Read/write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
AT32UC3A 27.6.8 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because CLK_SMC has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
AT32UC3A 27.6.8.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 27-33 on page 399. The external device may not be fast enough to support such timings. Figure 27-34 illustrates the recommended procedure to properly switch from one mode to the other. Figure 27-33.
AT32UC3A Figure 27-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PM CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE 1 1 1 2 3 2 NCS SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 27.6.9 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the MODE register (PMEN field).
AT32UC3A Figure 27-35. Page Mode Read Protocol (Address MSB and LSB are defined in Table 27-5) CLK_SMC A[MSB] A[LSB] NRD tpa tsa NCS tsa D[15:0] NCS_RD_PULSE NRD_PULSE NRD_PULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the PULSE register.
AT32UC3A 27.6.9.3 Page Mode Restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. 27.6.9.4 Sequential and Non-sequential Accesses If the chip select and the MSB of addresses as defined in Table 27-5 are identical, then the current access lies in the same page as the previous one, and no page break occurs.
AT32UC3A 27.7 User Interface The SMC is programmed using the registers listed in Table 27-7. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 27-7, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the MODE registers. SMC Register Mapping Table 27-7.
AT32UC3A 27.7.1 Setup Register Register Name: SETUP[0 ..
AT32UC3A 27.7.2 Pulse Register Register Name: PULSE[0..
AT32UC3A 27.7.3 Cycle Register Register Name: CYCLE[0..3] Access Type: Read/Write Offset: 0x10 x CS_number + 0x08 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE • NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle.
AT32UC3A 27.7.4 MODE Register Register Name: MODE[0..3] Access Type: Read/Write Offset: 0x10 x CS_number + 0x0C Reset Value: – 31 30 – – 23 22 21 20 – – – TDF_MODE 15 14 13 – – 7 6 – 29 28 PS 12 DBW 5 – 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 TDF_CYCLES 11 10 9 8 – – – BAT 3 2 1 0 – WRITE_MOD E READ_MODE – • PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes. Page size settings. Table 27-8.
AT32UC3A external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. • Data Bus Width (DBW) DBW Data Bus Width 0 0 8-bit bus 0 1 16-bit bus 1 0 32-bit bus 1 1 Reserved • BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
AT32UC3A – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD. 0: The read operation is controlled by the NCS signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
AT32UC3A 28. SDRAM Controller (SDRAMC) Rev: 2.0.1.1 28.1 Features • Numerous Configurations Supported • • • • • • 28.
AT32UC3A 28.3 Block Diagram Figure 28-1. SDRAM Controller Block Diagram PIO Controller SDRAMC Chip Select SDCK Memory Controller SDCKE SDCS SDRAMC Interrupt BA[1:0] RAS PMC SDRAMC MCK CAS SDWE NBS[3:0] SDRAMC_A[12:0] D[31:0] User Interface Peripheral Bus 28.4 I/O Lines Description Table 28-1.
AT32UC3A 28.5 Application Example 28.5.1 Hardware Interface Figure 28-2 shows an example of SDRAM device connection to the SDRAM Controller using a 32-bit data bus width. Figure 28-3 shows an example of SDRAM device connection using a 16bit data bus width. It is important to note that these examples are given for a direct connection of the devices to the SDRAM Controller, without External Bus Interface or PIO Controller multiplexing. Figure 28-2.
AT32UC3A 28.5.2 Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register. The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user. Table 28-2 to Table 28-7 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated. 28.5.2.
AT32UC3A 28.5.2.2 16-bit Memory Data Bus Width Table 28-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 Bk[1:0] 1 3 1 2 1 1 1 0 9 8 7 6 Row[10:0] Bk[1:0] 4 3 2 1 M 0 M 0 Column[9:0] Row[10:0] 0 M 0 Column[8:0] Row[10:0] Bk[1:0] 5 Column[7:0] Row[10:0] Bk[1:0] Table 28-6.
AT32UC3A 28.6 Product Dependencies 28.6.1 SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, ...), number of column, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register.
AT32UC3A Figure 28-4. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μsec 28.6.2 Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function.
AT32UC3A 28.7 Functional Description 28.7.1 SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out.
AT32UC3A For a single access or an incremented burst of unspecified length, the SDRAM Controller anticipates the next access. While the last value of the column is returned by the SDRAM Controller on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance.
AT32UC3A Figure 28-7. Read Burst with Boundary Row Access TRP = 3 TRCD = 3 CAS = 2 SDCS SDCK Row n SDRAMC_A[12:0] col a col b col c col d Row m col a col b col c col d col e RAS CAS SDWE D[31:0] 28.7.4 Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically.
AT32UC3A Figure 28-8. Refresh Cycle Followed by a Read Access tRP = 3 tRC = 8 tRCD = 3 CAS = 2 SDCS SDCK Row n Row m col c col d SDRAMC_A[12:0] col a RAS CAS SDWE D[31:0] (input) 28.7.5 Dnb Dnc Dnd Dma Power Management Three low-power modes are available: • Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM Controller. Current drained by the SDRAM is very low. • Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller.
AT32UC3A After initialization, as soon as PASR/DS/TCSR fields are modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR/DS/TCSR bits are updated before entry into self-refresh mode. The SDRAM device must remain in self-refresh mode for a minimum period of tRAS and may remain in self-refresh mode for an indefinite period. This is described in Figure 28-9. Figure 28-9.
AT32UC3A Figure 28-10. Low-power Mode Behavior TRCD = 3 CAS = 2 Low Power Mode SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f RAS CAS SDCKE D[31:0] (input) 28.7.5.3 Dna Dnb Dnc Dnd Dne Dnf Deep Power-down Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
AT32UC3A Figure 28-11.
AT32UC3A 28.8 SDRAM Controller User Interface Table 28-8.
AT32UC3A 28.8.1 SDRAMC Mode Register Register Name: MR Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 MODE • MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. Table 28-9. MODE Description 0 0 0 Normal mode.
AT32UC3A 28.8.2 SDRAMC Refresh Timer Register Register Name: TR Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 COUNT 3 2 COUNT • COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
AT32UC3A 28.8.3 SDRAMC Configuration Register Register Name: CR Access Type: Read/Write Reset Value: 0x852372C0 31 30 29 28 27 26 TXSR 23 22 21 20 19 18 TRCD 15 24 17 16 9 8 TRP 14 13 12 11 10 TRC 7 DBW 25 TRAS TWR 6 5 CAS 4 NB 3 2 NR 1 0 NC • NC: Number of Column Bits Reset value is 8 column bits. NC Column Bits 0 0 8 0 1 9 1 0 10 1 1 11 • NR: Number of Row Bits Reset value is 11 row bits.
AT32UC3A • CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed. CAS CAS Latency (Cycles) 0 0 Reserved 0 1 1 1 0 2 1 1 3 • DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. • TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
AT32UC3A 28.8.4 SDRAMC High Speed Register Register Name: HSR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DA • DA: Decode Cycle Enable A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus. The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
AT32UC3A 28.8.5 SDRAMC Low Power Register Register Name: LPR Access Type: Read/Write Reset Value: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 9 7 – 6 5 PASR TIMEOUT DS 4 3 – 8 TCSR 2 – 1 0 LPCB • LPCB: Low-power Configuration Bits 00 Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.
AT32UC3A After initialization, as soon as DS field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in self-refresh mode. • TIMEOUT: Time to define when low-power mode is enabled 00 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. 01 The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
AT32UC3A 28.8.6 SDRAMC Interrupt Enable Register Register Name: IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt.
AT32UC3A 28.8.7 SDRAMC Interrupt Disable Register Register Name: IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt.
AT32UC3A 28.8.8 SDRAMC Interrupt Mask Register Register Name: IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled.
AT32UC3A 28.8.9 SDRAMC Interrupt Status Register Register Name: ISR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read.
AT32UC3A 28.8.10 SDRAMC Memory Device Register Register Name: MDR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 MD • MD: Memory Device Type 00 SDRAM 01 Low-power SDRAM 10 Reserved 11 Reserved.
AT32UC3A 29. Ethernet MAC (MACB) Rev: 1.1.2.5 29.1 Features • • • • • • • • • • • • • • • • • • • • • 29.2 Compatible with IEEE Standard 802.
AT32UC3A 29.3 Block Diagram Figure 29-1. MACB Block Diagram Address Checker Peripheral Bus Slave Register Interface Statistics Registers Control Registers MDIO DMA Interface RX FIFO TX FIFO Ethernet Receive MII/RMII High Speed Bus Master Ethernet Transmit 29.4 Product Dependencies 29.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
AT32UC3A 29.4.3 Interrupt The MACB interface has an interrupt line connected to the Interrupt Controller. Handling the MACB interrupt requires programming the interrupt controller before configuring the MACB. 29.5 Functional Description Figure 29-1 on page 438 illustrates the different blocks of the MACB module. The control registers drive the MDIO interface, setup DMA activity, start frame transmission and select modes of operation such as full- or half-duplex.
AT32UC3A Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (12 bytes) of data. At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 60 MHz master clock this takes 100 ns, making the bus latency requirement 860 ns. 29.5.1.
AT32UC3A Receive Buffer Descriptor Entry (Continued) Table 29-1. Bit Function 20 19:17 Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier) VLAN priority (only valid if bit 21 is set) 16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set) 15 End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. 14 Start of frame - when set the buffer contains the start of a frame.
AT32UC3A For CRC errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors.
AT32UC3A point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. Note that disabling receive does not have the same effect on the receive queue pointer. Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start bit of the network control register.
AT32UC3A Transmit Buffer Descriptor Entry (Continued) Table 29-2. Bit Function 16 No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame. 15 Last buffer. When set, this bit indicates the last buffer in the current frame has been reached. 14:11 Reserved 10:0 Length of buffer 29.5.2 Transmit Block This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol.
AT32UC3A its current contents and regardless of the state of the configuration register bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. If bit 13 is set in the network configuration register and the value of the pause time register is non-zero, no new frame is transmitted until the pause time register has decremented to zero.
AT32UC3A After transmission, no interrupts are generated and the only statistics register that is incremented is the pause frames transmitted register. 29.5.4 Receive Block The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and stores the frames destination address for use by the address checking block. If, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block.
AT32UC3A The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB. Preamble 55 SFD D5 DA (Octet0 - LSB) 21 DA(Octet 1) 43 DA(Octet 2) 65 DA(Octet 3) 87 DA(Octet 4) A9 DA (Octet5 - MSB) CB SA (LSB) 00 SA 00 SA 00 SA 00 SA 00 SA (MSB) 43 SA (LSB) 21 The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown.
AT32UC3A hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^
AT32UC3A 29.5.11 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 29-4. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame.
AT32UC3A The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in Table 29-5. Pin Configuration Table 29-5.
AT32UC3A 29.6 Programming Interface 29.6.1 Initialization 29.6.1.1 Configuration Initialization of the MACB configuration (e.g. frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register later in this document. 29.6.1.2 Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory.
AT32UC3A 29.6.1.3 Transmit Buffer List Transmit data is read from the system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 29-2 on page 443) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2.
AT32UC3A 29.6.1.7 Receiving Frames When a frame is received and the receive circuits are enabled, the MACB checks the address and, in the following cases, the frame is written to system memory: • if it matches one of the four specific address registers. • if it matches the hash address function. • if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. • if the MACB is configured to copy all frames. • if the EAM is asserted before four words have been loaded into the receive FIFO.
AT32UC3A 29.7 Ethernet MAC (MACB) User Interface Table 29-6.
AT32UC3A Table 29-6.
AT32UC3A 29.7.1 Network Control Register Register Name: NCR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 TZQ 11 TPF 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: LoopBack Local connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
AT32UC3A • TSTART: Start transmission Writing one to this bit starts transmission. • THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends. • TPF: Transmit pause frame Writing one to this bit transmits a pause frame with the pause quantum from the transmit pause quantum register at the next available transmitter idle time.
AT32UC3A 29.7.2 Network Configuration Register Register Name: NCFGR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 15 14 13 PAE 12 RTY 11 10 9 EAE 8 BIG 5 NBC 4 CAF 3 JFRAME 2 Bit rate 1 FD 0 SPD RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
AT32UC3A • CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations). CLK MDC 00 MCK divided by 8 (MCK up to 20 MHz) 01 MCK divided by 16 (MCK up to 40 MHz) 10 MCK divided by 32 (MCK up to 80 MHz) 11 MCK divided by 64 (MCK up to 160 MHz) • RTY: Retry test Must be set to zero for normal operation.
AT32UC3A 29.7.3 Network Status Register Register Name: NSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 - • MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0 = The PHY logic is running. 1 = The PHY management logic is idle (i.e., has completed).
AT32UC3A 29.7.4 Transmit Status Register Register Name: TSR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
AT32UC3A 29.7.5 Receive Buffer Queue Pointer Register Register Name: RBQP Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
AT32UC3A 29.7.6 Transmit Buffer Queue Pointer Register Register Name: TBQP Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
AT32UC3A 29.7.7 Receive Status Register Register Name: RSR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
AT32UC3A 29.7.8 Interrupt Status Register Register Name: ISR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 - 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
AT32UC3A 29.7.
AT32UC3A Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt. • RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
AT32UC3A 29.7.10 Interrupt Disable Register Register Name: IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 - 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt. • RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
AT32UC3A 29.7.11 Interrupt Mask Register Register Name: IMR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 - 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
AT32UC3A 29.7.12 PHY Maintenance Register Register Name: MAN Access Type: 31 Read/Write 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 17 16 PHYA 20 REGA 19 18 12 11 10 9 8 3 2 1 0 CODE DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written. • REGA: Register Address Specifies the register in the PHY to access.
AT32UC3A 29.7.13 Pause Time Register Register Name: PTR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
AT32UC3A 29.7.14 Hash Register Bottom Register Name: HRB Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See ”Hash Addressing” on page 447.
AT32UC3A 29.7.15 Hash Register Top Register Name: HRT Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 63:32 of the hash address register. See ”Hash Addressing” on page 447.
AT32UC3A 29.7.16 Specific Address 1 Bottom Register Register Name: SA1B Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
AT32UC3A 29.7.17 Specific Address 1 Top Register Register Name: SA1T Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
AT32UC3A 29.7.18 Specific Address 2 Bottom Register Register Name: SA2B Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
AT32UC3A 29.7.19 Specific Address 2 Top Register Register Name: SA2T Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
AT32UC3A 29.7.20 Specific Address 3 Bottom Register Register Name: SA3B Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
AT32UC3A 29.7.21 Specific Address 3 Top Register Register Name: SA3T Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
AT32UC3A 29.7.22 Specific Address 4 Bottom Register Register Name: SA4B Access Type: 31 Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
AT32UC3A 29.7.23 Specific Address 4 Top Register Register Name: SA4T Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
AT32UC3A 29.7.24 Type ID Checking Register Register Name: TID Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID checking For use in comparisons with received frames TypeID/Length field.
AT32UC3A 29.7.25 Transmit Pause Quantum Register Register Name: TPQ Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TPQ 7 6 5 4 TPQ • TPQ: Transmit Pause Quantum Used in hardware generation of transmitted pause frames as value for pause quantum.
AT32UC3A 29.7.26 User Input/Output Register Register Name: USRIO Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 2 1 0 – – – – 3 TX_PAUSE_ ZERO TX_PAUSE EAM RMII • RMII When set, this bit enables the MII operation mode. When reset, it selects the RMII mode.
AT32UC3A 29.7.27 Wake-on-LAN Register Register Name: WOL Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 MTI 18 SA1 17 ARP 16 MAG 15 14 13 12 11 10 9 8 3 2 1 0 IP 7 6 5 4 IP • IP: ARP request IP address Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake-on-LAN event. A value of zero does not generate an event, even if this is matched by the received frame.
AT32UC3A 29.7.28 MACB Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7, WESTAT, in the network control register, NCR, must be set. The statistics register block contains the following registers. 29.7.28.
AT32UC3A 29.7.28.3 Single Collision Frames Register Register Name: SCF Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 29.7.28.
AT32UC3A 29.7.28.5 Frames Received OK Register Register Name: FRO Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
AT32UC3A 29.7.28.
AT32UC3A 29.7.28.9 Late Collisions Register Register Name: LCOL Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 29.7.28.
AT32UC3A 29.7.28.11 Transmit Underrun Errors Register Register Name: TUND Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented. 29.7.28.
AT32UC3A 29.7.28.13 Receive Resource Errors Register Register Name: RRE Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 29.7.28.
AT32UC3A 29.7.28.15 Receive Symbol Errors Register Register Name: RSE Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
AT32UC3A 29.7.28.
AT32UC3A 29.7.28.19 SQE Test Errors Register Register Name: STE Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 29.7.28.
AT32UC3A 29.7.28.21 Transmitted Pause Frames Register Register Name: TPF Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TPF 7 6 5 4 TPF • TPF: Transmitted Pause Frames A 16-bit register counting the number of pause frames transmitted.
AT32UC3A 30. USB On-The-Go Interface (USBB) Rev: 3.1.1.1 30.1 Features • • • • • • • 30.2 USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s 7 Pipes/Endpoints 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels On-Chip Transceivers Including Pull-Ups/Pull-downs.
AT32UC3A Table 30-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM Pipe/Endpoint Mnemonic Size Nb.
AT32UC3A 30.3 Block Diagram The USB controller provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). The USB controller requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock generated from one of the power manager oscillators, optionally through one of the power manager PLLs. The 48 MHz clock is used to generate a 12 MHz full-speed (or 1.
AT32UC3A 30.4 Application Block Diagram Depending on the USB operating mode (device-only, reduced-host or OTG mode) and the power source (bus-powered or self-powered), there are different typical hardware implementations. 30.4.1 30.4.1.1 Device Mode Bus-Powered Device Figure 30-2. Bus-Powered Device Application Block Diagram VDD 3.3 V Regulator USB USB Connector USB_VBOF VBUS VBUS DD+ D- 39 Ω ± 1% D+ 39 Ω ± 1% USB_ID ID GND 30.4.1.2 Self-Powered Device Figure 30-3.
AT32UC3A 30.4.2 Host and OTG Modes Figure 30-4. Host and OTG Application Block Diagram VDD 5 V DC/DC Generator USB USB Connector USB_VBOF VBUS VBUS DD+ 39 Ω ± 1% 39 Ω ± 1% USB_ID DD+ ID GND 30.5 I/O Lines Description Table 30-3.
AT32UC3A 30.6 Product Dependencies 30.6.1 I/O Lines The USB_VBOF and USB_ID pins are multiplexed with GPIO lines and may also be multiplexed with lines of other peripherals. In order to use them with the USB, the programmer must first program the GPIO controller to assign them to their USB peripheral functions. Moreover, if USB_ID is used, the GPIO controller must be configured to enable the internal pull-up resistor of its pin.
AT32UC3A 30.7 Functional Description 30.7.1 USB General Operation 30.7.1.1 Introduction After a hardware reset, the USB controller is disabled. When enabled, the USB controller runs either in device mode or in host mode according to the ID detection. If the USB_ID pin is not connected to ground, the ID bit is set by hardware (the internal pull-up resistor of the USB_ID pin must be enabled by the GPIO controller) and device mode is engaged.
AT32UC3A 30.7.1.3 Interrupts One interrupt vector is assigned to the USB interface. Figure 30-6 shows the structure of the USB interrupt system. Figure 30-6. Interrupt System USBSTA.IDTI USBCON.IDTE USBSTA.VBUSTI USBCON.VBUSTE USBSTA.SRPI USBCON.SRPE USBSTA.VBERRI USBCON.VBERRE USBSTA.BCERRI USB General Interrupt USBCON.BCERRE USBSTA.ROLEEXI USBCON.ROLEEXE USBSTA.HNPERRI USBCON.HNPERRE USBSTA.STOI USBCON.STOE UESTAX.TXINI UECONX.TXINE UESTAX.RXOUTI UECONX.RXOUTE UESTAX.RXSTPI UECONX.RXSTPE UESTAX.
AT32UC3A See Section 30.7.2.17 on page 520 and Section 30.7.3.13 on page 528 for further details about device and host interrupts. There are two kinds of general interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). The processing general interrupts are: •the ID Transition interrupt (IDTI); •the VBus Transition interrupt (VBUSTI); •the SRP interrupt (SRPI); •the Role Exchange interrupt (ROLEEXI).
AT32UC3A •the VBus Transition interrupt (VBUSTI); •the Wake-Up interrupt (WAKEUP); •the Host Wake-Up interrupt (HWUPI). 30.7.1.4.6 USB Suspend mode : In peripheral mode, the UDINT.SUSP bit indicates that the usb line is in the suspend mode. In this case, the USB Data transceiver is automatically set in suspend mode to reduce the consumption. 30.7.1.5 Speed Control 30.7.1.5.
AT32UC3A Disabling a pipe (PENX = 0) or an endpoint (EPENX = 0) resets neither its ALLOC bit nor its configuration (PBK/EPBK, PSIZE/EPSIZE, PTOKEN/EPDIR, PTYPE/EPTYPE, PEPNUM, INTFRQ). To free its memory, the firmware should clear its ALLOC bit. The ki+1 pipe/endpoint memory window then slides down and its data is lost. Note that the following pipe/endpoint memory windows (from ki+2) do not slide. Figure 30-8 illustrates the allocation and reorganization of the DPRAM in a typical example. Figure 30-8.
AT32UC3A 30.7.1.7 Pad Suspend Figure 30-9 shows the pad behavior. Figure 30-9. Pad Behavior USBE = 1 & DETACH = 0 & Suspend Idle USBE = 0 | DETACH = 1 | Suspend Active • In the Idle state, the pad is put in low power consumption mode. • In the Active state, the pad is working. Figure 30-10 illustrates the pad events leading to a PAD state change. Figure 30-10.
AT32UC3A 30.7.1.8 Customizing of OTG Timers It is possible to refine some OTG timers thanks to the TIMPAGE and TIMVALUE bit-fields, as shown by Figure 30-4. Customizing of OTG Timers Table 30-4. TIMVALUE TIMPAGE 00b: AWaitVrise Time-Out ([OTG] Chapter 6.6.5.1) 01b: VbBusPulsing Time-Out ([OTG] Chapter 5.3.4) 10b: PdTmOutCnt Time-Out ([OTG] Chapter 5.3.2) 11b: SRPDetTmOut Time-Out ([OTG] Chapter 5.3.
AT32UC3A •it is cleared when the voltage on the VBUS pad is lower than 1.4 V. In host mode, the VBUS bit follows an hysteresis based on Session_valid and Va_Vbus_valid: •it is set when the voltage on the VBUS pad is higher than or equal to 4.4 V; •it is cleared when the voltage on the VBUS pad is lower than 1.4 V. The VBus Transition interrupt (VBUSTI) is raised on each transition of the VBUS bit. The VBUS bit is effective whether the USB macro is enabled or not. 30.7.1.
AT32UC3A 30.7.2 30.7.2.1 USB Device Operation Introduction In device mode, the USB controller supports full- and low-speed data transfers. In addition to the default control endpoint, six endpoints are provided, which can be configured with the types isochronous, bulk or interrupt, as described in Table 30-1 on page 497. The device mode starts in the Idle state, so the pad consumption is reduced to the minimum. 30.7.2.2 Power-On and Reset Figure 30-13 describes the USB controller device mode main states.
AT32UC3A 30.7.2.4 Endpoint Reset An endpoint can be reset at any time by setting its EPRSTX bit in the UERST register. This is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This resets: •the internal state machine of this endpoint; •the receive and transmit bank FIFO counters; •all the registers of this endpoint (UECFGX, UESTAX, UECONX), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and its Data Toggle Sequence bit-field (DTSEQ).
AT32UC3A See Section 30.7.1.6 on page 506 for more details about DPRAM management. 30.7.2.
AT32UC3A • The firmware may then set the RMWKUP bit to send an upstream resume to the host for a remote wake-up. This will automatically be done by the controller after 5 ms of inactivity on the USB bus. • When the controller sends the upstream resume, the Upstream Resume interrupt (UPRSM) is raised and SUSP is cleared by hardware. • RMWKUP is cleared by hardware at the end of the upstream resume.
AT32UC3A •the Received OUT Data interrupt (RXOUTI) which is raised when a new OUT packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank; •the Transmitted IN Data interrupt (TXINI) which is raised when the current bank is ready to accept a new IN packet and which shall be cleared by firmware to send the packet. 30.7.2.11.2 Control Write Figure 30-15 shows a control write transaction.
AT32UC3A The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the following software algorithm: set TXINI wait for RXOUTI OR TXINI if RXOUTI, then clear flag and return if TXINI, then continue Once the OUT status stage has been received, the USB controller waits for a SETUP request. The SETUP request has priority over any other request and has to be ACKed. This means that any other flag should be cleared and the FIFO reset when a SETUP is received.
AT32UC3A Figure 30-18. Example of an IN Endpoint with 2 Data Banks DATA (bank 0) IN ACK IN DATA (bank 1) ACK HW TXINI FIFOCON SW SW write data to CPU BANK 0 SW write data to CPU BANK 1 SW SW write data to CPU BANK0 30.7.2.12.
AT32UC3A Figure 30-19. Abort Algorithm Endpoint Abort Disable the TXINI interrupt. TXINEC = 1 NBUSYBK == 0? Yes No EPRSTX = 1 Abort is based on the fact that no bank is busy, i.e. that nothing has to be sent. KILLBKS = 1 Yes KILLBK == 1? Kill the last written bank. Wait for the end of the procedure. No Abort Done 30.7.2.13 Management of OUT Endpoints 30.7.2.13.1 Overview OUT packets are sent by the host.
AT32UC3A Figure 30-20. Example of an OUT Endpoint with 1 Data Bank DATA (bank 0) OUT NAK ACK DATA (bank 0) OUT HW ACK HW RXOUTI SW SW read data from CPU BANK 0 FIFOCON read data from CPU BANK 0 SW Figure 30-21. Example of an OUT Endpoint with 2 Data Banks OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW RXOUTI HW SW read data from CPU BANK 0 FIFOCON SW SW read data from CPU BANK 1 30.7.2.13.
AT32UC3A An underflow can not occur during OUT stage on a CPU action, since the firmware may read only if the bank is not empty (RXOUTI = 1 or RWALL = 1). An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. An underflow can not occur during IN stage on a CPU action, since the firmware may write only if the bank is not full (TXINI = 1 or RWALL = 1). 30.7.2.
AT32UC3A 30.7.2.17.2 Endpoint Interrupts The processing device endpoint interrupts are: •the Transmitted IN Data interrupt (TXINI); •the Received OUT Data interrupt (RXOUTI); •the Received SETUP interrupt (RXSTPI); •the Short Packet interrupt (SHORTPACKET); •the Number of Busy Banks interrupt (NBUSYBK).
AT32UC3A 30.7.3 30.7.3.1 USB Host Operation Description of Pipes For the USB controller in host mode, the term “pipe” is used instead of “endpoint” (used in device mode). A host pipe corresponds to a device endpoint, as described by the Figure 30-22 from the USB specification. Figure 30-22. USB Communication Flow In host mode, the USB controller associates a pipe to a device endpoint, considering the device configuration descriptors. 30.7.3.
AT32UC3A The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e. when the host mode does not generate the “Start of Frame”. In this state, the USB consumption is minimal. The host mode exits the Suspend state when starting to generate the SOF over the USB line. 30.7.3.3 Device Detection A device is detected by the USB controller host mode when D+ or D- is no longer tied low, i.e. when the device D+ or D- pull-up resistor is connected.
AT32UC3A Figure 30-24. Pipe Activation Algorithm Pipe Activation PENX = 1 Enable the pipe. UPCFGX Configure the pipe: - interrupt request frequency; - endpoint number; - type; - token; - size; - number of banks. Allocate the configured DPRAM banks. INTFRQ PEPNUM PTYPE PTOKEN PSIZE PBK ALLOC CFGOK == 1? Yes Pipe Activated Test if the pipe configuration is correct.
AT32UC3A interrupt (HWUPI). If the non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received interrupt (RXRSMI) is raised. The firmware has to generate a Downstream Resume within 1 ms and for at least 20 ms by setting the RESUME bit. It is mandatory to set SOFE before setting RESUME to enter the Ready state, else RESUME will have no effect. 30.7.3.
AT32UC3A Figure 30-25. Example of an IN Pipe with 1 Data Bank DATA (bank 0) IN ACK DATA (bank 0) IN HW RXINI ACK HW SW SW read data from CPU BANK 0 FIFOCON read data from CPU BANK 0 SW Figure 30-26. Example of an IN Pipe with 2 Data Banks IN DATA (bank 0) ACK IN DATA (bank 1) HW RXINI HW SW read data from CPU BANK 0 FIFOCON 30.7.3.11 ACK SW SW read data from CPU BANK 1 Management of OUT Pipes OUT packets are sent by the host.
AT32UC3A Figure 30-27. Example of an OUT Pipe with 1 Data Bank DATA (bank 0) OUT ACK OUT HW TXOUTI SW SW write data to CPU BANK 0 FIFOCON write data to CPU BANK 0 SW SW Figure 30-28. Example of an OUT Pipe with 2 Data Banks and no Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW SW write data to CPU BANK 0 FIFOCON SW write data to CPU BANK 1 SW write data to CPU BANK0 SW Figure 30-29.
AT32UC3A 30.7.3.13 Interrupts See the structure of the USB host interrupt system on Figure 30-6 on page 504. There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). 30.7.3.13.
AT32UC3A 30.7.4 USB DMA Operation USB packets of any length may be transferred when required by the USB controller. These transfers always feature sequential addressing. These two characteristics mean that in case of high USB controller throughput, both HSB ports will benefit from “incrementing burst of unspecified length” since the average access latency of HSB slaves can then be reduced.
AT32UC3A 30.8 USB User Interface Table 30-5.
AT32UC3A Table 30-5.
AT32UC3A Table 30-5.
AT32UC3A Table 30-5.
AT32UC3A Table 30-5.
AT32UC3A Table 30-5.
AT32UC3A Table 30-5.
AT32UC3A Table 30-6.
AT32UC3A 30.8.1 USB General Registers 30.8.1.
AT32UC3A Clear to disable the Role Exchange interrupt (ROLEEXI). • HNPERRE: HNP Error Interrupt Enable Set to enable the HNP Error interrupt (HNPERRI). Clear to disable the HNP Error interrupt (HNPERRI). • STOE: Suspend Time-Out Interrupt Enable Set to enable the Suspend Time-Out interrupt (STOI). Clear to disable the Suspend Time-Out interrupt (STOI). • VBUSHWC: VBus Hardware Control Set to disable the hardware control over the USB_VBOF output pin.
AT32UC3A • FRZCLK: Freeze USB Clock Set to disable the clock inputs (the resume detection is still active). This reduces power consumption. Unless explicitly stated, all registers then become read-only. Clear to enable the clock inputs. Note that this bit can be set/cleared even if USBE = 0 or FRZCLK = 1. Disabling the USB controller (by clearing the USBE bit) does not reset this bit, but this freezes the clock inputs whatever its value. • USBE: USB Macro Enable Set to enable the USB controller.
AT32UC3A 30.8.1.2 USB General Status Register (USBSTA) Offset: 0x0804 Register Name: USBSTA Access Type: Read-Only Reset Value: 0x00000400 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 10 ID ru 1 9 VBUSRQ ru 0 8 – 2 SRPI ru 0 1 VBUSTI ru 0 0 IDTI ru 0 7 STOI ru 0 6 HNPERRI ru 0 0 0 11 VBUS ru 0 5 ROLEEXI ru 0 4 BCERRI ru 0 3 VBERRI ru 0 SPEED ru • IDTI: ID Transition Interrupt Flag Asynchronous interrupt.
AT32UC3A • VBERRI: VBus Error Interrupt Flag In host mode, set by hardware when a VBus drop has been detected. This triggers a USB interrupt if VBERRE = 1. Shall be cleared by software (by setting the VBERRIC bit) to acknowledge the interrupt. Note that if a VBus problem occurs, then the VBERRI interrupt is generated even if the USB macro does not go to an error state because of VBUSHWC = 1.
AT32UC3A 30.8.1.3 USB General Status Clear Register (USBSTACLR) Offset: 0x0808 Register Name: USBSTACLR Access Type: Write-Only Read Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 VBUSRQC w 0 8 – 7 STOIC w 0 6 HNPERRIC w 0 5 ROLEEXIC w 0 4 BCERRIC w 0 3 VBERRIC w 0 2 SRPIC w 0 1 VBUSTIC w 0 0 IDTIC w 0 • IDTIC: ID Transition Interrupt Flag Clear Set to clear IDTI.
AT32UC3A Clearing has no effect. Always read as 0. • ROLEEXIC: Role Exchange Interrupt Flag Clear Set to clear ROLEEXI. Clearing has no effect. Always read as 0. • HNPERRIC: HNP Error Interrupt Flag Clear Set to clear HNPERRI. Clearing has no effect. Always read as 0. • STOIC: Suspend Time-Out Interrupt Flag Clear Set to clear STOI. Clearing has no effect. Always read as 0. • VBUSRQC: VBus Request Clear Set to clear VBUSRQ. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.1.
AT32UC3A Clearing has no effect. Always read as 0. • ROLEEXIS: Role Exchange Interrupt Flag Set Set to set ROLEEXI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • HNPERRIS: HNP Error Interrupt Flag Set Set to set HNPERRI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • STOIS: Suspend Time-Out Interrupt Flag Set Set to set STOI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.1.5 USB IP Version Register (UVERS) Offset: 0x0818 Register Name: UVERS Access Type: Read-Only Read Value: 0x00000260 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 16 0 17 METAL_FIX_NUM r 0 10 9 8 1 0 15 14 13 12 11 VERSION_NUM r 0 7 6 0 2 5 4 3 2 VERSION_NUM r 6 0 • VERSION_NUM: IP Version Number This field indicates the version number of the USB macro IP, encoded with 1 version digit per nibble, e.g. 0x0260 for version 2.6.0.
AT32UC3A 30.8.1.
AT32UC3A • DMA_BUFFER_SIZE: DMA Buffer Size This field indicates the size of the DMA buffer: DMA_BUFFER_SIZE DMA Buffer Size 0 16 bits 1 24 bits • DMA_FIFO_WORD_DEPTH: DMA FIFO Depth in Words This field indicates the DMA FIFO depth controller in words: DMA_FIFO_WORD_DEPTH DMA FIFO Depth in Words 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 ... 1 1 1 1 15 • FIFO_MAX_SIZE: Maximal FIFO Size This field indicates the maximal FIFO size, i.e.
AT32UC3A 30.8.1.
AT32UC3A 30.8.1.8 USB IP Name Register 1 (UNAME1) Offset: 0x0824 Register Name: UNAME1 Access Type: Read-Only Read Value: 0x48555342 (“HUSB”) 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UNAME1 r “H” 23 22 21 20 UNAME1 r “U” 15 14 13 12 UNAME1 r “S” 7 6 5 4 UNAME1 r “B” • UNAME1: IP Name Part 1 This field indicates the 1st part of the ASCII-encoded name of the USB macro IP.
AT32UC3A 30.8.1.9 USB IP Name Register 2 (UNAME2) Offset: 0x0828 Register Name: UNAME2 Access Type: Read-Only Read Value: 0x004F5447 (“\0OTG“) 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UNAME2 r “\0“ 23 22 21 20 UNAME2 r “O“ 15 14 13 12 UNAME2 r “T“ 7 6 5 4 UNAME2 r “G“ • UNAME2: IP Name Part 2 This field indicates the 2nd part of the ASCII-encoded name of the USB macro IP.
AT32UC3A 30.8.1.10 USB Finite State Machine Status Register (USBFSM) Offset: 0x082C Register Name: USBFSM Access Type: Read-Only Read Value: 0x00000009 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 0 0 0 0 0 0 0 0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 0 0 0 0 0 0 0 0 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 0 0 0 0 0 0 0 0 7 - 6 - 5 - 4 - 3 2 1 0 0 0 0 0 1 0 1 DRDSTATE r 0 • DRDSTATE This field indicates the state of the USB controller.
AT32UC3A USBFSM Description 11 b_wait_begin_hnp : In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. 12 b_wait_discharge : In this state, the B-device waits for the data usb line to discharge (100 us) before becoming Host. 13 b_wait_acon : In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. 14 b_host : In this state, the B-device acts as the Host.
AT32UC3A 30.8.2 USB Device Registers 30.8.2.1 USB Device General Control Register (UDCON) Offset: 0x0000 Register Name: UDCON Access Type: Read/Write Reset Value: 0x00000100 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LS 11 – 10 – 9 RMWKUP 8 DETACH rwu 0 rw 1 2 1 0 0 0 0 rw 0 7 ADDEN rwu 0 6 5 4 0 0 0 3 UADD rwu 0 • UADD: USB Address Set to configure the device address.
AT32UC3A Clear to unforce the low-speed mode. Then, the full-speed mode is active. Note that this bit can be set/cleared even if USBE = 0 or FRZCLK = 1. Disabling the USB controller (by clearing the USBE bit) does not reset this bit.
AT32UC3A 30.8.2.
AT32UC3A Note that this interrupt is generated even if the clock is frozen by the FRZCLK bit. • EORSM: End of Resume Interrupt Flag Set by hardware when the USB controller detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if EORSME = 1. Shall be cleared by software (by setting the EORSMC bit) to acknowledge the interrupt. • UPRSM: Upstream Resume Interrupt Flag Set by hardware when the USB controller sends a resume signal called “Upstream Resume”.
AT32UC3A 30.8.2.3 USB Device Global Interrupt Clear Register (UDINTCLR) Offset: 0x0008 Register Name: UDINTCLR Access Type: Write-Only Read Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UPRSMC w 0 5 EORSMC w 0 4 WAKEUPC w 0 3 EORSTC w 0 2 SOFC w 0 1 – 0 SUSPC w 0 • SUSPC: Suspend Interrupt Flag Clear Set to clear SUSP. Clearing has no effect. Always read as 0.
AT32UC3A Clearing has no effect. Always read as 0. • UPRSMC: Upstream Resume Interrupt Flag Clear Set to clear UPRSM. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.
AT32UC3A Clearing has no effect. Always read as 0. • UPRSMS: Upstream Resume Interrupt Flag Set Set to set UPRSM, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • DMAXINTS, X in [1..6]: DMA Channel X Interrupt Flag Set Set to set DMAXINT, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.
AT32UC3A • EPXINTE, X in [0..6]: Endpoint X Interrupt Enable Set by software (by setting the EPXINTES bit) to enable the Endpoint X interrupt (EPXINT). Clear by software (by setting the EPXINTEC bit) to disable the Endpoint X interrupt (EPXINT). • DMAXINTE, X in [1..6]: DMA Channel X Interrupt Enable Set by software (by setting the DMAXINTES bit) to enable the DMA Channel X interrupt (DMAXINT). Clear by software (by setting the DMAXINTEC bit) to disable the DMA Channel X interrupt (DMAXINT).
AT32UC3A 30.8.2.
AT32UC3A Clearing has no effect. Always read as 0. • UPRSMEC: Upstream Resume Interrupt Enable Clear Set to clear UPRSME. Clearing has no effect. Always read as 0. • EPXINTEC, X in [0..6]: Endpoint X Interrupt Enable Clear Set to clear EPXINTE. Clearing has no effect. Always read as 0. • DMAXINTEC, X in [1..6]: DMA Channel X Interrupt Enable Clear Set to clear DMAXINTE. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.
AT32UC3A Clearing has no effect. Always read as 0. • UPRSMES: Upstream Resume Interrupt Enable Set Set to set UPRSME. Clearing has no effect. Always read as 0. • EPXINTES, X in [0..6]: Endpoint X Interrupt Enable Set Set to set EPXINTE. Clearing has no effect. Always read as 0. • DMAXINTES, X in [1..6]: DMA Channel X Interrupt Enable Set Set to set DMAXINTE. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.8 USB Device Frame Number Register (UDFNUM) Offset: 0x0020 Register Name: UDFNUM Access Type: Read-Only Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FNCERR ru 0 14 – 13 12 11 10 9 8 7 6 0 0 FNUM ru 0 0 0 0 0 0 5 FNUM ru 0 4 3 2 – 1 – 0 – 0 0 • FNUM: Frame Number Set by hardware. These bits are the 11-bit frame number information. They are provided in the last received SOF packet.
AT32UC3A 30.8.2.9 USB Endpoint Enable/Reset Register (UERST) Offset: 0x001C Register Name: UERST Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 EPRST6 rwu 0 21 EPRST5 rwu 0 20 EPRST4 rwu 0 19 EPRST3 rwu 0 18 EPRST2 rwu 0 17 EPRST1 rwu 0 16 EPRST0 rwu 0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 EPEN6 rw 0 5 EPEN5 rw 0 4 EPEN4 rw 0 3 EPEN3 rw 0 2 EPEN2 rw 0 1 EPEN1 rw 0 0 EPEN0 rw 0 • EPENX, X in [0..
AT32UC3A 30.8.2.10 USB Endpoint X Configuration Register (UECFGX) Offset: 0x0100 + X . 0x04 Register Name: UECFGX, X in [0..6] Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 – 9 AUTOSW rwu 0 8 EPDIR rwu 0 2 1 ALLOC rwu 0 0 – 7 – 6 5 EPSIZE rwu 0 0 EPTYPE rwu 0 0 4 3 EPBK rwu 0 0 0 • ALLOC: Endpoint Memory Allocate Set to allocate the endpoint memory.
AT32UC3A • EPSIZE: Endpoint Size Set to select the size of each endpoint bank: EPSIZE Endpoint Size 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 128 bytes 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes Cleared by hardware upon receiving a USB reset (except for the endpoint 0).
AT32UC3A 30.8.2.11 USB Endpoint X Status Register (UESTAX) Offset: 0x0130 + X . 0x04 Register Name: UESTAX, X in [0..
AT32UC3A Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt and to free the bank. For isochronous, bulk and interrupt OUT endpoints: Set by hardware at the same time as FIFOCON when the current bank is full. This triggers an EPXINT interrupt if RXOUTE = 1. Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO. The software then reads from the FIFO and clears the FIFOCON bit to free the bank.
AT32UC3A Shall be cleared by software (by setting the OVERFIC bit) to acknowledge the interrupt. • STALLEDI: STALLed Interrupt Flag Set by hardware to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by setting the STALLRQS bit). This triggers an EPXINT interrupt if STALLEDE = 1. Shall be cleared by software (by setting the STALLEDIC bit) to acknowledge the interrupt.
AT32UC3A For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers an EPXINT interrupt if NBUSYBKE = 1. Note that when the FIFOCON bit is cleared (by setting the FIFOCONC bit) to validate a new bank, this field is updated 2 or 3 clock cycles later to calculate the address of the next bank. An EPXINT interrupt is triggered if : - for IN endpoint, NBUSYBKE=1 and all the banks are free.
AT32UC3A For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host. For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software from the endpoint. Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt flag.
AT32UC3A 30.8.2.12 USB Endpoint X Status Clear Register (UESTAXCLR) Offset: 0x0160 + X . 0x04 Register Name: UESTAXCLR, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKINIC: NAKed IN Interrupt Flag Clear Set to clear NAKINI. Clearing has no effect. Always read as 0. • OVERFIC: Overflow Interrupt Flag Clear Set to clear OVERFI. Clearing has no effect. Always read as 0. • STALLEDIC: STALLed Interrupt Flag Clear Set to clear STALLEDI. Clearing has no effect. Always read as 0. • CRCERRIC: CRC Error Interrupt Flag Clear Set to clear CRCERRI. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.13 USB Endpoint X Status Set Register (UESTAXSET) Offset: 0x0190 + X . 0x04 Register Name: UESTAXSET, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKINIS: NAKed IN Interrupt Flag Set Set to set NAKINI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • OVERFIS: Overflow Interrupt Flag Set Set to set OVERFI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • STALLEDIS: STALLed Interrupt Flag Set Set to set STALLEDI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.14 USB Endpoint X Control Register (UECONX) Offset: 0x01C0 + X . 0x04 Register Name: UECONX, X in [0..
AT32UC3A • OVERFE: Overflow Interrupt Enable Set by software (by setting the OVERFES bit) to enable the Overflow interrupt (OVERFI). Clear by software (by setting the OVERFEC bit) to disable the Overflow interrupt (OVERFI). • STALLEDE: STALLed Interrupt Enable Set by software (by setting the STALLEDES bit) to enable the STALLed interrupt (STALLEDI). Clear by software (by setting the STALLEDEC bit) to disable the STALLed interrupt (STALLEDI).
AT32UC3A Clear by software (by setting the FIFOCONC bit) to free the current bank and to switch to the next bank. • EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable Set by software (by setting the EPDISHDMAS bit) to pause the on-going DMA channel X transfer on any Endpoint X interrupt (EPXINT), whatever the state of the Endpoint X Interrupt Enable bit (EPXINTE). The software then has to acknowledge or to disable the interrupt source (e.g.
AT32UC3A 30.8.2.15 USB Endpoint X Control Clear Register (UECONXCLR) Offset: 0x0220 + X . 0x04 Register Name: UECONXCLR, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKINEC: NAKed IN Interrupt Enable Clear Set to clear NAKINE. Clearing has no effect. Always read as 0. • OVERFEC: Overflow Interrupt Enable Clear Set to clear OVERFE. Clearing has no effect. Always read as 0. • STALLEDEC: STALLed Interrupt Enable Clear Set to clear STALLEDE. Clearing has no effect. Always read as 0. • CRCERREC: CRC Error Interrupt Enable Clear Set to clear CRCERRE. Clearing has no effect. Always read as 0.
AT32UC3A • STALLRQC: STALL Request Clear Set to clear STALLRQ. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.16 USB Endpoint X Control Set Register (UECONXSET) Offset: 0x01F0 + X . 0x04 Register Name: UECONXSET, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKINES: NAKed IN Interrupt Enable Set Set to set NAKINE. Clearing has no effect. Always read as 0. • OVERFES: Overflow Interrupt Enable Set Set to set OVERFE. Clearing has no effect. Always read as 0. • STALLEDES: STALLed Interrupt Enable Set Set to set STALLEDE. Clearing has no effect. Always read as 0. • CRCERRES: CRC Error Interrupt Enable Set Set to set CRCERRE. Clearing has no effect. Always read as 0.
AT32UC3A Always read as 0. • RSTDTS: Reset Data Toggle Set Set to set RSTDT. Clearing has no effect. Always read as 0. • STALLRQS: STALL Request Set Set to set STALLRQ. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.2.17 USB Device DMA Channel X Next Descriptor Address Register (UDDMAX_NEXTDESC) Offset: 0x0310 + (X - 1) . 0x10 Register Name: UDDMAX_NEXTDESC, X in [1..
AT32UC3A 30.8.2.18 USB Device DMA Channel X HSB Address Register (UDDMAX_ADDR) Offset: 0x0314 + (X - 1) . 0x10 Register Name: UDDMAX_ADDR, X in [1..
AT32UC3A 30.8.2.19 USB Device DMA Channel X Control Register (UDDMAX_CONTROL) Offset: 0x0318 + (X - 1) . 0x10 Register Name: UDDMAX_CONTROL, X in [1..
AT32UC3A • EOT_IRQ_EN: End of USB Transfer Interrupt Enable Set this bit to enable the end of usb OUT data transfer interrupt. This interrupt is generated only if the BUFF_CLOSE_IN_EN bit is set. Clear this bit to disable this interrupt. • EOBUFF_IRQ_EN: End of Buffer Interrupt Enable Set this bit to enable the end of buffer interrupt. This interrupt is generated when the channel byte count reaches zero. Clear this bit to disable this interrupt.
AT32UC3A 30.8.2.20 USB Device DMA Channel X Status Register (UDDMAX_STATUS) Offset: 0x031C + (X - 1) . 0x10 Register Name: UDDMAX_STATUS, X in [1..
AT32UC3A • CH_BYTE_CNT: Channel Byte Count This field gives the current number of bytes still to be transferred for this buffer. This field is decremented at each dma access. This field is reliable (stable) only if the CH_EN flag is 0.
AT32UC3A 30.8.3 USB Host Registers 30.8.3.
AT32UC3A 30.8.3.
AT32UC3A • HWUPI: Host Wake-Up Interrupt Flag Asynchronous interrupt. Set by hardware in the following cases : – The Host controller is in the suspend mode (SOFE=0) and an upstream resume from the Peripheral is detected. – The Host controller is in the suspend mode (SOFE=0) and a Peripheral disconnection is detected. – The Host controller is in the Idle state (VBUSRQ=0, no VBus is generated), and an OTG SRP event initiated by the Peripheral is detected.
AT32UC3A 30.8.3.3 USB Host Global Interrupt Clear Register (UHINTCLR) Offset: 0x0408 Register Name: UHINTCLR Access Type: Write-Only Read Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 HWUPIC w 0 5 HSOFIC w 0 4 RXRSMIC w 0 3 RSMEDIC w 0 2 RSTIC w 0 1 DDISCIC w 0 0 DCONNIC w 0 • DCONNIC: Device Connection Interrupt Flag Clear Set to clear DCONNI. Clearing has no effect.
AT32UC3A Clearing has no effect. Always read as 0. • HSOFIC: Host Start of Frame Interrupt Flag Clear Set to clear HSOFI. Clearing has no effect. Always read as 0. • HWUPIC: Host Wake-Up Interrupt Flag Clear Set to clear HWUPI. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.3.
AT32UC3A Clearing has no effect. Always read as 0. • HSOFIS: Host Start of Frame Interrupt Flag Set Set to set HSOFI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • HWUPIS: Host Wake-Up Interrupt Flag Set Set to set HWUPI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • DMAXINTS, X in [1..6]: DMA Channel X Interrupt Flag Set Set to set DMAXINT, what may be useful for test or debug purposes. Clearing has no effect.
AT32UC3A 30.8.3.
AT32UC3A • HWUPIE: Host Wake-Up Interrupt Enable Set by software (by setting the HWUPIES bit) to enable the Host Wake-up Interrupt (HWUPI). Clear by software (by setting the HWUPIEC bit) to disable the Host Wake-up Interrupt (HWUPI). • PXINTE, X in [0..6]: Pipe X Interrupt Enable Set by software (by setting the PXINTES bit) to enable the Pipe X Interrupt (PXINT). Clear by software (by setting the PXINTEC bit) to disable the Pipe X Interrupt (PXINT). • DMAXINTE, X in [1..
AT32UC3A 30.8.3.
AT32UC3A Clearing has no effect. Always read as 0. • HSOFIEC: Host Start of Frame Interrupt Enable Clear Set to clear HSOFIEC. Clearing has no effect. Always read as 0. • HWUPIEC: Host Wake-Up Interrupt Enable Clear Set to clear HWUPIEC. Clearing has no effect. Always read as 0. • PXINTEC, X in [0..6]: Pipe X Interrupt Enable Clear Set to clear PXINTEC. Clearing has no effect. Always read as 0. • DMAXINTEC, X in [1..6]: DMA Channel X Interrupt Enable Clear Set to clear DMAXINTEC. Clearing has no effect.
AT32UC3A 30.8.3.
AT32UC3A Clearing has no effect. Always read as 0. • HSOFIES: Host Start of Frame Interrupt Enable Set Set to set HSOFIE. Clearing has no effect. Always read as 0. • HWUPIES: Host Wake-Up Interrupt Enable Set Set to set HWUPIE. Clearing has no effect. Always read as 0. • PXINTES, X in [0..6]: Pipe X Interrupt Enable Set Set to set PXINTE. Clearing has no effect. Always read as 0. • DMAXINTES, X in [1..6]: DMA Channel X Interrupt Enable Set Set to set DMAXINTE. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.3.8 USB Host Frame Number Register (UHFNUM) Offset: 0x0420 Register Name: UHFNUM Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 0 0 0 10 9 8 FLENHIGH ru 0 0 0 0 0 15 – 14 – 13 12 11 7 6 0 0 FNUM rwu 0 0 0 0 0 0 5 FNUM rwu 0 4 3 2 – 1 – 0 – 0 0 • FNUM: Frame Number The value contained in this register is the current SOF number. This value can be modified by software.
AT32UC3A 30.8.3.
AT32UC3A 30.8.3.
AT32UC3A 30.8.3.11 USB Pipe Enable/Reset Register (UPRST) Offset: 0x0041C Register Name: UPRST Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 PRST6 rwu 0 21 PRST5 rwu 0 20 PRST4 rwu 0 19 PRST3 rwu 0 18 PRST2 rwu 0 17 PRST1 rwu 0 16 PRST0 rwu 0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 PEN6 rw 0 5 PEN5 rw 0 4 PEN4 rw 0 3 PEN3 rw 0 2 PEN2 rw 0 1 PEN1 rw 0 0 PEN0 rw 0 • PENX, X in [0..
AT32UC3A 30.8.3.12 USB Pipe X Configuration Register (UPCFGX) Offset: 0x0500 + X . 0x04 Register Name: UPCFGX, X in [0..
AT32UC3A • PSIZE: Pipe Size Set to select the size of each pipe bank: PSIZE Endpoint Size 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 128 bytes 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes Cleared by hardware upon sending a USB reset. • PTOKEN: Pipe Token Set to select the endpoint token: PTOKEN Endpoint Direction 00 SETUP 01 IN 10 OUT 11 reserved • AUTOSW: Automatic Switch Set to automatically switch bank when it is ready.
AT32UC3A • INTFRQ: Pipe Interrupt Request Frequency These bits are the maximum value in millisecond of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe. Cleared by hardware upon sending a USB reset.
AT32UC3A 30.8.3.13 USB Pipe X Status Register (UPSTAX) Offset: 0x0530 + X . 0x04 Register Name: UPSTAX, X in [0..
AT32UC3A • OVERFI: Overflow Interrupt Flag Set by hardware when the current Pipe has received more data than the maximum length of the current Pipe. An interrupt is triggered if the OVERFIE bit is set. Shall be cleared by software (by setting the OVERFIC bit). • RXSTALLDI: Received STALLed Interrupt Flag For all endpoints but isochronous. Set by hardware when a STALL handshake has been received on the current bank of the Pipe. The Pipe is automatically frozen.
AT32UC3A • CURRBK: Current Bank For non-control pipe, set by hardware to indicate the number of the current bank. CURRBK Current Bank 0 0 Bank0 0 1 Bank1 1 0 Bank2 1 1 Reserved Note that this field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt flag. • RWALL: Read/Write Allowed For OUT pipe, set by hardware when the current bank is not full, i.e. the software can write further data into the FIFO.
AT32UC3A 30.8.3.14 USB Pipe X Status Clear Register (UPSTAXCLR) Offset: 0x0560 + X . 0x04 Register Name: UPSTAXCLR, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • OVERFIC: Overflow Interrupt Flag Clear Set to clear OVERFI. Clearing has no effect. Always read as 0. • RXSTALLDIC: Received STALLed Interrupt Flag Clear Set to clear RXSTALLDI. Clearing has no effect. Always read as 0. • CRCERRIC: CRC Error Interrupt Flag Clear Set to clear CRCERRI. Clearing has no effect. Always read as 0. • SHORTPACKETIC: Short Packet Interrupt Flag Clear Set to clear SHORTPACKETI. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.3.15 USB Pipe X Status Set Register (UPSTAXSET) Offset: 0x0590 + X . 0x04 Register Name: UPSTAXSET, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKEDIS: NAKed Interrupt Flag Set Set to set NAKEDI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • OVERFIS: Overflow Interrupt Flag Set Set to set OVERFI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0. • RXSTALLDIS: Received STALLed Interrupt Flag Set Set to set RXSTALLDI, what may be useful for test or debug purposes. Clearing has no effect. Always read as 0.
AT32UC3A 30.8.3.16 USB Pipe X Control Register (UPCONX) Offset: 0x05C0 + X . 0x04 Register Name: UPCONX, X in [0..
AT32UC3A • OVERFIE: Overflow Interrupt Enable Set by software (by setting the OVERFIES bit) to enable the Overflow interrupt (OVERFIE). Clear by software (by setting the OVERFIEC bit) to disable the Overflow interrupt (OVERFIE). • RXSTALLDE: Received STALLed Interrupt Enable Set by software (by setting the RXSTALLDES bit) to enable the Received STALLed interrupt (RXSTALLDE). Clear by software (by setting the RXSTALLDEC bit) to disable the Received STALLed interrupt (RXSTALLDE).
AT32UC3A 30.8.3.17 USB Pipe X Control Clear Register (UPCONXCLR) Offset: 0x0620 + X . 0x04 Register Name: UPCONXCLR, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKEDEC: NAKed Interrupt Enable Clear Set to clear NAKEDE. Clearing has no effect. Always read as 0. • OVERFIEC: Overflow Interrupt Enable Clear Set to clear OVERFIE. Clearing has no effect. Always read as 0. • RXSTALLDEC: Received STALLed Interrupt Enable Clear Set to clear RXSTALLDE. Clearing has no effect. Always read as 0. • CRCERREC: CRC Error Interrupt Enable Clear Set to clear CRCERRE. Clearing has no effect. Always read as 0.
AT32UC3A Clearing has no effect. Always read as 0.
AT32UC3A 30.8.3.18 USB Pipe X Control Set Register (UPCONXSET) Offset: 0x05F0 + X . 0x04 Register Name: UPCONXSET, X in [0..
AT32UC3A Clearing has no effect. Always read as 0. • NAKEDES: NAKed Interrupt Enable Set Set to set NAKEDE. Clearing has no effect. Always read as 0. • OVERFIES: Overflow Interrupt Enable Set Set to set OVERFIE. Clearing has no effect. Always read as 0. • RXSTALLDES: Received STALLed Interrupt Enable Set Set to set RXSTALLDE. Clearing has no effect. Always read as 0. • CRCERRES: CRC Error Interrupt Enable Set Set to set CRCERRE. Clearing has no effect. Always read as 0.
AT32UC3A Clearing has no effect. Always read as 0.
AT32UC3A 30.8.3.19 USB Pipe X IN Request Register (UPINRQX) Offset: 0x0650 + X . 0x04 Register Name: UPINRQX, X in [0..6] Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INMODE rw 0 7 6 5 4 3 2 1 0 0 0 0 0 INRQ rwu 0 0 0 0 • INRQ: IN Request Number before Freeze Enter the number of IN transactions before the USB controller freezes the pipe.
AT32UC3A 30.8.3.20 USB Pipe X Error Register (UPERRX) Offset: 0x0680 + X . 0x04 Register Name: UPERRX, X in [0..6] Access Type: Read/Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 4 CRC16 rwu 0 3 TIMEOUT rwu 0 2 PID rwu 0 1 DATAPID rwu 0 0 DATATGL rwu 0 COUNTER rwu 0 0 • DATATGL: Data Toggle Error Set by hardware when a data toggle error has been detected.
AT32UC3A 30.8.3.21 USB Host DMA Channel X Next Descriptor Address Register (UHDMAX_NEXTDESC) Offset: 0x0710 + (X - 1) . 0x10 Register Name: UHDMAX_NEXTDESC, X in [1..
AT32UC3A 30.8.3.22 USB Host DMA Channel X HSB Address Register (UHDMAX_ADDR) Offset: 0x0714 + (X - 1) . 0x10 Register Name: UHDMAX_ADDR, X in [1..
AT32UC3A 30.8.3.23 USB Host DMA Channel X Control Register (UHDMAX_CONTROL) Offset: 0x0718 + (X - 1) . 0x10 Register Name: UHDMAX_CONTROL, X in [1..
AT32UC3A 30.8.3.24 USB Host DMA Channel X Status Register (UHDMAX_STATUS) Offset: 0x071C + (X - 1) . 0x10 Register Name: UHDMAX_STATUS, X in [1..
AT32UC3A 30.8.4 USB Pipe/Endpoint X FIFO Data Register (USB_FIFOX_DATA) Note that this register can be accessed even if USBE = 0 or FRZCLK = 1. Disabling the USB controller (by clearing the USBE bit) does not reset the DPRAM.
AT32UC3A 31. Timer/Counter (TC) Rev: 2.2.2.1 31.
AT32UC3A 31.3 Block Diagram Figure 31-1.
AT32UC3A 31.4 Pin Name List Table 31-2. 31.5 TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Product Dependencies 31.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 31.5.
AT32UC3A Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5. The Peripherals Chapter details the connection of these clock sources. • External clock signals: XC0, XC1 or XC2. The Peripherals Chapter details the connection of these clock sources. This selection is made by the TCCLKS bits in the TC Channel Mode Register .
AT32UC3A (LDBSTOP = 1 in CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in CMR). The start and the stop commands have effect only if the clock is enabled. Figure 31-3. Clock Control Selected Clock Trigger CLKSTA CLKEN Q Q S CLKDIS S R R Counter Clock 31.6.1.4 Stop Event Disable Event TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation.
AT32UC3A If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 31.6.
32058K AVR32-01/12 MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS LDRBS INT
AT32UC3A 31.6.3 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in CMR).
32058K AVR32-01/12 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Q CLKSTA Compare RA = Register A TC1_SR Timer/Counter Channel Edge Detector EEVTEDG SWTRG CLKI Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TI
AT32UC3A 31.6.3.2 WAVSEL = 00 When WAVSEL = 00, the value of CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CV is reset. Incrementation of CV starts again and the cycle continues. See Figure 31-6. An external event trigger or a software trigger can reset the value of CV. It is important to note that the trigger may occur at any time. See Figure 31-7. RC Compare cannot be programmed to generate a trigger in this configuration.
AT32UC3A Figure 31-7. WAVSEL= 00 with trigger Counter cleared by compare match with 0xFFFF Counter Value 0xFFFF Counter cleared by trigger RC RB RA Time Waveform Examples TIOB TIOA 31.6.3.3 WAVSEL = 10 When WAVSEL = 10, the value of CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of CV has been reset, it is then incremented and so on. See Figure 31-8.
AT32UC3A Figure 31-9. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 31.6.3.4 WAVSEL = 01 When WAVSEL = 01, the value of CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 31-10. A trigger such as an external event or a software trigger can modify CV at any time.
AT32UC3A Figure 31-10. WAVSEL = 01 Without Trigger Counter decremented by compare match with 0xFFFF Counter Value 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 31-11. WAVSEL = 01 With Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Time Waveform Examples TIOB TIOA 31.6.3.5 WAVSEL = 11 When WAVSEL = 11, the value of CV is incremented from 0 to RC.
AT32UC3A Figure 31-12. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 31-13. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples Time TIOB TIOA 31.6.3.
AT32UC3A If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers.
AT32UC3A 31.7 Timer Counter (TC) User Interface Table 31-3. Offset TC Global Memory Map Channel/Register Name Access Reset Value 0x00 TC Channel 0 See Table 31-4 0x40 TC Channel 1 See Table 31-4 0x80 TC Channel 2 See Table 31-4 0xC0 TC Block Control Register BCR Write-only – 0xC4 TC Block Mode Register BMR Read/Write 0 BCR (Block Control Register) and BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 31-4.
AT32UC3A 31.7.1 TC Block Control Register Register Name: BCR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
AT32UC3A 31.7.
AT32UC3A 31.7.3 TC Channel Control Register Register Name: CCR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command 0 = No effect.
AT32UC3A 31.7.
AT32UC3A 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock.
AT32UC3A 31.7.
AT32UC3A 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection EEVT Note: Signal selected as external event TIOB Direction 0 0 TIOB input(1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output 1.
AT32UC3A • ACPA: RA Compare Effect on TIOA ACPA Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB BCPB 0 Effect 0 none 662 32058K AVR32-01/12
AT32UC3A BCPB Effect 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 663 32058K AVR32-01/12
AT32UC3A 31.7.6 TC Counter Value Register Register Name: CV Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
AT32UC3A 31.7.7 TC Register A Register Name: RA Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
AT32UC3A 31.7.8 TC Register B Register Name: RB Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
AT32UC3A 31.7.9 TC Register C Register Name: RC Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
AT32UC3A 31.7.10 TC Status Register Register Name: SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 MTIOB 17 MTIOA 16 CLKSTA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt flag for the corresponding interrupts.
AT32UC3A • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high.
AT32UC3A 31.7.11 TC Interrupt Enable Register Register Name: IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt flag for the corresponding interrupts. • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt.
AT32UC3A 31.7.12 TC Interrupt Disable Register Register Name: IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt flag for the corresponding interrupts. • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt.
AT32UC3A 31.7.13 TC Interrupt Mask Register Register Name: IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt flag for the corresponding interrupts. • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled.
AT32UC3A 32. Pulse Width Modulation Controller (PWM) Rev: 1.3.0.1 32.
AT32UC3A 32.3 Block Diagram Figure 32-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Channel Period PWMx Update Clock Selector Duty Cycle Comparator PWMx Counter PIO PWM0 Channel Period PWM0 Update Clock Selector Power Manager MCK Clock Generator Duty Cycle Comparator PWM0 Counter PB Interface Interrupt Generator Interrupt Controller Peripheral Bus 32.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 32-1.
AT32UC3A 32.5 Product Dependencies 32.5.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. Not all PWM outputs may be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. 32.5.
AT32UC3A 32.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 7 channels. – Clocked by the system clock, MCK, the clock generator module provides 13 clocks. – Each channel can independently choose one of the clock generator outputs. – Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 32.6.1 PWM Clock Generator Figure 32-2.
AT32UC3A The clock generator is divided in three blocks: – a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 – two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (MR).
AT32UC3A - If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: (-----------------------------X × CPRD )MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (----------------------------------------CRPD × DIVA )( C
AT32UC3A Figure 32-4. Non Overlapped Center Aligned Waveforms No overlap PWM0 PWM1 Period Note: 1. See Figure 32-5 on page 680 for a detailed description of center aligned waveforms. When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
AT32UC3A Figure 32-5.
AT32UC3A 32.6.3 32.6.3.1 PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the CMRx register) • Configuration of the period for each channel (CPRD in the CPRDx register).
AT32UC3A Figure 32-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in ISR Register according to the enabled channel(s).
AT32UC3A 32.6.3.4 Interrupts Depending on the interrupt mask in the IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the IER register. A channel interrupt is disabled by setting the corresponding bit in the IDR register.
AT32UC3A 32.7 Pulse Width Modulation (PWM) Controller User Interface 32.7.1 Register Mapping Table 32-2.
AT32UC3A 32.7.2 PWM Mode Register Register Name: MR Access Type: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 PREB 19 18 17 16 11 10 9 8 1 0 DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
AT32UC3A 32.7.3 PWM Enable Register Register Name: ENA Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
AT32UC3A 32.7.4 PWM Disable Register Register Name: DIS Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
AT32UC3A 32.7.5 PWM Status Register Register Name: SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
AT32UC3A 32.7.6 PWM Interrupt Enable Register Register Name: IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
AT32UC3A 32.7.7 PWM Interrupt Disable Register Register Name: IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
AT32UC3A 32.7.8 PWM Interrupt Mask Register Register Name: IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
AT32UC3A 32.7.9 PWM Interrupt Status Register Register Name: ISR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period since the last read of the ISR register. 1 = At least one new channel period since the last read of the ISR register.
AT32UC3A 32.7.
AT32UC3A • CPD: Channel Update Period 0 = Writing to the CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the CUPDx will modify the period at the next period start event.
AT32UC3A 32.7.11 PWM Channel Duty Cycle Register Register Name: CDTYx Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 20 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (CPRx).
AT32UC3A 32.7.12 PWM Channel Period Register Register Name: CPRDx Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 20 bits (internal channel counter size) are significant.
AT32UC3A 32.7.13 PWM Channel Counter Register Register Name: CCNTx Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the ENA register). • the counter reaches CPRD value defined in the CPRDx register if the waveform is left aligned.
AT32UC3A 32.7.14 PWM Channel Update Register Register Name: CUPDx Access Type: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 20 bits (internal channel counter size) are significant.
AT32UC3A 33. Analog-to-Digital Converter (ADC) Rev: 1.0.0.3 33.1 Features • Integrated Multiplexer Offering Up to Eight Independent Analog Inputs • Individual Enable and Disable of Each Channel • Hardware or Software Trigger – External Trigger Pin – Timer Counter Outputs (Corresponding TIOA Trigger) • PDC Support • Possibility of ADC Timings Configuration • Sleep Mode and Conversion Sequencer – Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels 33.
AT32UC3A 33.3 Block Diagram Figure 33-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC Trigger Selection TRIGGER Control Logic ADC Interrupt INTC VDDANA ADVREF HSB ADDedicated Analog Inputs PDC ADAD- Analog Inputs Multiplexed With I/O lines AD- PIO AD- Successive Approximation Register Analog-to-Digital Converter User Interface Peripheral Bridge PB AD- GND 33.4 I/O Lines Description Table 33-1.
AT32UC3A 33.5.2 Analog Inputs The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the CHER register . By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND. 33.5.3 Power Manager The ADC is automatically clocked after the first conversion in Normal Mode.
AT32UC3A 33.6 Functional Description 33.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the MR register and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the MR register. The ADC clock range is between CLK_ADC/2, if PRESCAL is 0, and CLK_ADC/128, if PRESCAL is set to 63 (0x3F).
AT32UC3A 33.6.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (CDR) of the current channel and in the ADC Last Converted Data Register (LCDR). The channel EOC bit in the Status Register (SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the CDR registers clears the corresponding EOC bit.
AT32UC3A If the CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in SR. The OVRE and GOVRE flags are automatically cleared when SR is read. Figure 33-3.
AT32UC3A 33.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the field TRGSEL in the Mode Register (MR).
AT32UC3A 33.6.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register MR. Warning: No input buffer amplifier to isolate the source is included in the ADC.
AT32UC3A 33.7 User Interface Table 33-2.
AT32UC3A 33.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 – – – – – – 1 START 0 SWRST • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset.
AT32UC3A 33.7.
AT32UC3A TRGSEL Selected TRGSEL 1 0 1 Internal Trigger 5, depending of chip integration 1 1 0 External trigger 1 1 1 Reserved • TRGEN: Trigger Enable TRGEN Selected TRGEN 0 Hardware triggers are disabled. Starting a conversion is only possible by software. 1 Hardware trigger selected by TRGSEL field is enabled.
AT32UC3A 33.7.3 Name: Channel Enable Register CHER Access Type: Write-only Offset: 0x10 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH2 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel(if implemented).
AT32UC3A 33.7.4 Name: Channel Disable Register CHDR Access Type: Write-only Offset: 0x14 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel(if implemented).
AT32UC3A 33.7.5 Name: Channel Status Register CHSR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled(if implemented). 1 = Corresponding channel is enabled(if implemented).
AT32UC3A 33.7.6 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x000C0000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – RXBUFF ENDRX GOVRE DRDY 15 14 13 12 11 10 9 8 OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • RXBUFF: RX Buffer Full 0 = RCR or RNCR have a value other than 0. 1 = Both RCR and RNCR have a value of 0.
AT32UC3A 33.7.7 Name: Last Converted Data Register LCDR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 7 6 5 4 3 2 LDATA 1 LDATA 8 0 • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
AT32UC3A 33.7.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – RXBUFF ENDRX GOVRE DRDY 15 14 13 12 11 10 9 8 OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
AT32UC3A 33.7.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – RXBUFF ENDRX GOVRE DRDY 15 14 13 12 11 10 9 8 OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
AT32UC3A 33.7.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – RXBUFF ENDRX GOVRE DRDY 15 14 13 12 11 10 9 8 OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The corresponding interrupt is disabled.
AT32UC3A 33.7.11 Name: Channel Data Register CDRx Access Type: Read-only Offset: 0x2C-0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 7 6 5 4 3 2 DATA 1 DATA 8 0 • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
AT32UC3A 33.7.12 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 9 8 – – – – 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] VERSION[7:0] 3 2 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
AT32UC3A 34. Audio Bitstream DAC (ABDAC) Rev: 1.0.1.1 34.1 Features • Digital Stereo DAC • Oversampled D/A conversion architecture – Oversampling ratio fixed 128x – FIR equalization filter – Digital interpolation filter: Comb4 – 3rd Order Sigma-Delta D/A converters • Digital bitstream outputs • Parallel interface • Connected to DMA Controller for background transfer without CPU intervention 34.
AT32UC3A 34.3 Block Diagram Figure 34-1. Functional Block Diagram Audio Bitstream DAC clk Clock Generator sample_clk bit_clk din1[15:0] Equalization FIR COMB (INT=128) Sigma-Delta DA-MOD bit_out1 din2[15:0] Equalization FIR COMB (INT=128) Sigma-Delta DA-MOD bit_out2 34.4 Pin Name List Table 34-1.
AT32UC3A 34.5.3 Clock Management The Audio Bitstream DAC needs a separate clock for the D/A conversion operation. This clock should be set up in the generic clock register in the power manager. The frequency of this clock must be 256 times the frequency of the desired samplerate (fs). For fs=48kHz this means that the clock must have a frequency of 12.288MHz. 34.5.4 Interrupts The Audio Bitstream DAC interface has an interrupt line connected to the interrupt controller.
AT32UC3A 34.6.2 Interpolation filter The interpolation filter interpolates from fs to 128fs. This filter is a 4th order Cascaded IntegratorComb filter, and the basic building blocks of this filter is a comb part and an integrator part. 34.6.3 Sigma Delta Modulator This part is a 3rd order Sigma Delta Modulator consisting of three differentiators (delta blocks), three integrators (sigma blocks) and a one bit quantizer.
AT32UC3A 34.7 Audio Bitstream DAC User Interface Register Mapping Table 34-2.
AT32UC3A 34.7.1 Audio Bitstream DAC Sample Data Register Name: SDR Access Type: Read-Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHANNEL1 23 22 21 20 15 14 13 12 CHANNEL1 CHANNEL0 7 6 5 4 CHANNEL0 • CHANNEL0: Sample Data for Channel 0 Signed 16-bit Sample Data for channel 0. When the SWAP bit in the DAC Control Register (CR) is set writing to the Sample Data Register (SDR) will cause the values written to CHANNEL0 and CHANNEL1 to be swapped.
AT32UC3A 34.7.2 Audio Bitstream DAC Control Register Name: CR Access Type: Read-Write 31 EN 23 15 7 - 30 SWAP 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • SWAP: Swap Channels 0: The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio Bitstream DAC Sample Data Register (SDR). 1: The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio Bitstream DAC Sample Data Register (SDR).
AT32UC3A 34.7.3 Audio Bitstream DAC Interrupt Mask Register Name: IMR Access Type: Read-only 31 23 15 7 - 30 22 14 6 - 29 TX_READY 21 13 5 - 28 UNDERRUN 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • UNDERRUN: Underrun Interrupt Mask 0: The Audio Bitstream DAC Underrun interrupt is disabled. 1: The Audio Bitstream DAC Underrun interrupt is enabled. • TX_READY: TX Ready Interrupt Mask 0: The Audio Bitstream DAC TX Ready interrupt is disabled.
AT32UC3A 34.7.4 Audio Bitstream DAC Interrupt Enable Register Name: IER Access Type: Write-only 31 23 15 7 - 30 22 14 6 - 29 TX_READY 21 13 5 - 28 UNDERRUN 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • UNDERRUN: Underrun Interrupt Enable 0: No effect. 1: Enables the Audio Bitstream DAC Underrun interrupt. • TX_READY: TX Ready Interrupt Enable 0: No effect. 1: Enables the Audio Bitstream DAC TX Ready interrupt.
AT32UC3A 34.7.5 Audio Bitstream DAC Interrupt Disable Register Name: IDR Access Type: Write-only 31 23 15 7 - 30 22 14 6 - 29 TX_READY 21 13 5 - 28 UNDERRUN 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • UNDERRUN: Underrun Interrupt Disable 0: No effect. 1: Disable the Audio Bitstream DAC Underrun interrupt. • TX_READY: TX Ready Interrupt Disable 0: No effect. 1: Disable the Audio Bitstream DAC TX Ready interrupt.
AT32UC3A 34.7.6 Audio Bitstream DAC Interrupt Clear Register Name: ICR Access Type: Write-only 31 23 15 7 - 30 22 14 6 - 29 TX_READY 21 13 5 - 28 UNDERRUN 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • UNDERRUN: Underrun Interrupt Clear 0: No effect. 1: Clear the Audio Bitstream DAC Underrun interrupt. • TX_READY: TX Ready Interrupt Clear 0: No effect. 1: Clear the Audio Bitstream DAC TX Ready interrupt.
AT32UC3A 34.7.7 Audio Bitstream DAC Interrupt Status Register Name: ISR Access Type: Read-only 31 23 15 7 - 30 22 14 6 - 29 TX_READY 21 13 5 - 28 UNDERRUN 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • UNDERRUN: Underrun Interrupt Status 0: No Audio Bitstream DAC Underrun has occured since the last time ISR was read or since reset. 1: At least one Audio Bitstream DAC Underrun has occured since the last time ISR was read or since reset.
AT32UC3A 34.8 Frequency Response Figure 34-2.
AT32UC3A 35. On-Chip Debug Rev: 1.3.0.0 35.1 35.2 Features • • • • • • • • Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.
AT32UC3A 35.3 Block diagram Figure 35-1. On-Chip Debug block diagram JTAG JTAG AUX On-Chip Debug Memory Service Unit Service Access Bus Transmit Queue Watchpoints Debug PC Debug Instruction Breakpoints CPU 35.4 Program Trace Internal SRAM HSB Bus Matrix Data Trace Ownership Trace Memories and peripherals Functional description 35.4.1 JTAG-based debug features A debugger can control all OCD features by writing OCD registers over the JTAG interface.
AT32UC3A Figure 35-2. JTAG-based debugger PC JTAG-based debug tool 10-pin IDC JTAG AVR32 35.4.1.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange data between the CPU and the JTAG master, both runtime as well as in debug mode. 35.4.1.
AT32UC3A 35.4.1.3 OCD Mode When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g. read out the register file by issuing mtdr instructions to the CPU, writing each register to the Debug Communication Channel OCD registers. 35.4.1.
AT32UC3A Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mictor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device. Table 35-1.
AT32UC3A The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 35.4.3.2 Program Trace Program trace allows the debugger to continuously monitor the program execution in the CPU.
AT32UC3A 35.4.3.7 Software Quality Analysis (SQA) Software Quality Analysis (SQA) deals with two important issues regarding embedded software development. Code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. Performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized.
AT32UC3A 36. JTAG and Boundary Scan Rev.: 2.0.0.2 36.1 36.2 Features • • • • IEEE1149.1 compliant JTAG Interface Boundary-Scan Chain for board-level testing Direct memory access and programming capabilities through JTAG interface On-Chip Debug access in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Overview Figure 36-1 on page 742 shows how the JTAG is connected in an AVR32 device. The TAP Controller is a state machine controlled by the TCK and TMS signals.
AT32UC3A 36.3 Block diagram Figure 36-1. JTAG and Boundary Scan access AVR32 device JTAG TAP JTAG master Boundary scan enable TAP Controller TCK TMS TDI TDO Data register scan enable Instruction Register Scan enable Instruction Register TMS TCK TDO TDI JTAG data registers JTAG device ID Register Bypass Reset Register ...
AT32UC3A 36.4 I/O Lines Description Table 36-1. I/O Lines Description Name Description Type TCK Test Clock Input. Fully asynchronous to system clock frequency. Input TMS Test Mode Select, sampled on rising TCK Input TDI Test Data In, sampled on rising TCK. Input TDO Test Data Out, driven on falling TCK. Output 36.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 36.5.
AT32UC3A Figure 36-2. TAP Controller State Diagram 1 Test-LogicReset 0 0 Run-Test/ Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 0 Capture-DR 1 1 0 Shift-DR 0 0 Shift-IR 1 1 Exit1-DR Exit1-IR 0 0 Pause-DR 1 Exit2-DR 0 0 Pause-IR 1 1 0 1 1 Update-DR 0 36.6.2 36.6.2.
AT32UC3A Figure 36-3. Scanning in JTAG instruction TCK TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI TMS TDI TDO 36.6.2.2 Instruction ImplDefined Scanning in/out data At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register - Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK.
AT32UC3A instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG interface for Boundary-Scan, the JTAG TCK clock is independent of the internal chip clock, which is not required to run. 36.6.4 Service Access Bus A number of private instructions are used to access Service Access Bus (SAB) resources. Each of these are described in detail in SAB address map in the Service Access Bus chapter.
AT32UC3A • A SYNC countdown completed. • A operation is cancelled by the CANCEL_ACCESS instruction. What to do if the busy bit is set: • During Shift-IR: The new instruction is selected, but the previous operation has not yet completed and will continue (unless the new instruction is CANCEL_ACCESS). You may continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy.
AT32UC3A Memory can be written while the CPU is executing, which can be utilized for debug purposes. When downloading a new program, the JTAG HALT instruction should be used to freeze the CPU, to prevent partially downloaded code from being executed. 36.7 JTAG Instruction Summary The implemented JTAG instructions in the AVR32 are shown in the table below. Table 36-2. Instruction OPCODE JTAG Instruction Summary Instruction Description 0x01 IDCODE Select the 32-bit ID register as data register.
AT32UC3A For description of what memory locations remain accessible, please refer to the SAB address map. Full access to these instructions is re-enabled when the security fuse is erased by the CHIP_ERASE JTAG instruction. Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 36.
AT32UC3A • Shift-DR: The Internal Scan Chain is shifted by the TCK input. • Update-DR: Data from the scan chain is applied to internal logic inputs. 36.8.5 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven from the Boundary-Scan Chain. The active states are: • Capture-DR: Loads a logic ‘0’ into the Bypass Register. • Shift-DR: Data is scanned from TDI to TDO through the Bypass register. 36.8.
AT32UC3A bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is 34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar". The following describes how to interpret the fields in the instruction description tables: Table 36-4. 36.9.2 Instruction description Instruction Description IR input value Shows the bit pattern to shift into IR in the Shift-IR state in order to select this instruction.
AT32UC3A For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 36-5. 36.9.
AT32UC3A For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 36-6. 36.9.
AT32UC3A Table 36-7. Size Field Semantics Size field value Access size Data alignment Halfword (16 bits) Address modulo 4 : data alignment 0: dddddddd dddddddd xxxxxxxx xxxxxxxx 1: Not allowed 2: xxxxxxxx xxxxxxxx dddddddd dddddddd 3: Not allowed 10 Word (32 bits) Address modulo 4 : data alignment 0: dddddddd dddddddd dddddddd dddddddd 1: Not allowed 2: Not allowed 3: Not allowed 11 Reserved N/A 01 Starting in Run-Test/Idle, SAB data are accessed in the following way: 1.
AT32UC3A Note: This instruction was previously known as MEMORY_ACCESS, and is provided for backwards compatibility. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, SAB data are accessed in the following way: 1. Select the DR Scan path. 2.
AT32UC3A 1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the first location. 2. Apply MEMORY_BLOCK_ACCESS in the IR Scan path. 3. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corresponding to the next byte, halfword, or word location). 4. For a read operation, scan out the contents of the next addressed location. For a write operation, scan in the new contents of the next addressed location. 5. Go to Update-DR. 6.
AT32UC3A 36.9.8 SYNC This instruction allows external debuggers and testers to measure the ratio between the external JTAG clock and the internal system clock. The SYNC data register is a 16-bit counter that counts down to zero using the internal system clock. The busy bit stays high until the counter reaches zero. Starting in Run-Test/Idle, SYNC instruction is used in the following way: 1. Select the DR Scan path. 2. Scan in an 16-bit counter value. 3. Go to Update-DR and re-enter Select-DR Scan. 4.
AT32UC3A devices without non-volatile memories this instruction does nothing, and appears to complete immediately. The erasing of non-volatile memories starts as soon as the CHIP_ERASE instruction is selected. The CHIP_ERASE instruction selects a 1 bit bypass data register. A chip erase operation should be performed as: 1. Scan in the HALT instruction 2. Scan in the value 1 to halt the CPU 3. Stay in Run-Test/Idle for 10 TCK cycles to let the halt command propagate properly 4.
AT32UC3A 16. Stay in Run-Test/Idle for 10 TCK cycles to let the command propagate properly - the device now runs with the new code. Table 36-15.
AT32UC3A 36.10 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. 36.10.1 Device Identification Register The Device Identification Register contains a unique identifier for each product.
AT32UC3A CPU CPU APP HSB and PB buses OCD On-Chip Debug logic and registers RSERVED No effect Note: This register is primarily intended for compatibility with other AVR32 devices. Certain operations may not function correctly when parts of the system are reset. It is generally recommended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side effects occur. 36.10.
AT32UC3A 37. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to Section 13. ”Power Manager (PM)” on page 53. 37.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source.
AT32UC3A 38. Electrical Characteristics 38.1 Absolute Maximum Ratings* Operating Temperature. Storage Temperature . -60°C to +150°C Voltage on Input Pin with respect to Ground except for PC00, PC01, PC02, PC03, PC04, PC05..........................................................-0.3V to 5.5V Voltage on Input Pin with respect to Ground for PC00, PC01, PC02, PC03, PC04, PC05.....................................................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE, VDDPLL) .
AT32UC3A 38.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. DC Characteristics Table 38-1. Symbol Parameter VVDDCOR Max Units DC Supply Core 1.65 1.95 V VVDDPLL DC Supply PLL 1.65 1.95 V VVDDIO DC Supply Peripheral I/Os 3.0 3.6 V VREF Analog reference voltage 2.6 3.6 V VIL Input Low-level Voltage -0.3 +0.
AT32UC3A 38.3 Regulator characteristics Table 38-2. Symbol Parameter VVDDIN Supply voltage (input) VVDDOUT Supply voltage (output) IOUT ISCR Electrical characteristics Condition Min. Typ. Max. Units 3 3.3 3.6 V 1.81 1.85 1.89 V Maximum DC output current with VVDDIN = 3.3V 100 mA Maximum DC output current with VVDDIN = 2.7V 90 mA Low Power mode (stop, deep stop or static) at TA =25°C Static Current of internal regulator Table 38-3.
AT32UC3A Table 38-7. 38.4.2 BOD Timing Symbol Parameter Test Conditions Typ. Max. Units. TBOD Minimum time with VDDCORE < VBOD to detect power failure Falling VDDCORE from 1.8V to 1.1V 300 800 ns POR Table 38-8. Electrical Characteristic Symbol Parameter Test Conditions VDDRR VDDCORE rise rate to ensure power-on-reset 0.01 VSSFR VDDCORE fall rate to ensure power-on-reset 0.
AT32UC3A 38.5 Power Consumption The values in Table 38-9 and Table 38-10 on page 769 are measured values of power consumption with operating conditions as follows: •VDDIO = 3.3V •VDDCORE = VDDPLL = 1.8V •TA = 25°C, TA = 85°C •I/Os are configured in input, pull-up enabled. Figure 38-1.
AT32UC3A These figures represent the power consumption measured on the power supplies. Table 38-9. Power Consumption for Different Modes Mode Conditions Active Typ : Ta =25 °C CPU running from flash (1). VDDIN=3.3 V. VDDCORE =1.8V. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated. GPIOs on internal pull-up. JTAG unconnected with ext pull-up. Idle Frozen Standby Typ.
AT32UC3A Table 38-9. Power Consumption for Different Modes Mode Conditions Typ. Unit Stop Typ : Ta = 25 °C. CPU is in stop mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are stopped on Amp0 47 uA on Amp1 40 uA on Amp0 36 uA Deepstop Typ : Ta = 25 °C.CPU is in deepstop mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground.
AT32UC3A • VDDCORE = 1.8V • Ambient Temperature = 25°C 38.6.1 CPU/HSB Clock Characteristics Table 38-11. Core Clock Waveform Parameters Symbol Parameter 1/(tCPCPU) CPU Clock Frequency tCPCPU CPU Clock Period 38.6.2 Conditions Min Max Units 66 MHz 15,15 ns PBA Clock Characteristics Table 38-12. PBA Clock Waveform Parameters Symbol Parameter 1/(tCPPBA) PBA Clock Frequency tCPPBA PBA Clock Period 38.6.
AT32UC3A 38.7.2 Main Oscillators Characteristics Table 38-15. Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal Oscillator Frequency CL1, CL2 Internal Load Capacitance (CL1 = CL2) Conditions Min 0.45 Max Unit 16 MHz 12 Duty Cycle 40 tST Startup Time 1/(tCPXIN) XIN Clock Frequency tCHXIN XIN Clock High Half-period 0.4 x tCPXIN tCLXIN XIN Clock Low Half-period 0.4 x tCPXIN CIN XIN Input Capacitance 38.7.3 Typ 50 8 MHz External clock Crystal 0.
AT32UC3A 38.8 ADC Characteristics Table 38-17. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency ADC Clock Frequency Startup Time Min Max Units 10-bit resolution mode 5 MHz 8-bit resolution mode 8 MHz Return from Idle Mode 20 µs Track and Hold Acquisition Time Typ 600 Conversion Time ADC Clock = 5 MHz ns 2 µs Conversion Time ADC Clock = 8 MHz 1.
AT32UC3A Table 38-21. Transfer Characteristics in 10-bit mode Parameter Conditions Min Resolution Typ Max 10 Units Bit Absolute Accuracy f=5MHz Integral Non-linearity f=5MHz 1.5 2 LSB f=5MHz 1 2 LSB 0.6 1 LSB Differential Non-linearity 3 f=2.
AT32UC3A 38.9 EBI Timings These timings are given for worst case process, T = 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 38-22. SMC Clock Signal. Symbol Parameter 1/(tCPSMC) SMC Controller Clock Frequency Note: Max(1) Units 1/(tcpcpu) MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 38-23.
AT32UC3A Table 38-24. SMC Read Signals with no Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC19 Data Setup before NRD High SMC20 Data Hold after NRD High 13.7 1 ns NRD Controlled (READ_MODE = 0) SMC21 Data Setup before NCS High SMC22 Data Hold after NCS High 13.3 0 ns Table 38-25. SMC Write Signals with Hold Settings Symbol Parameter Min Units NRD Controlled (READ_MODE = 1) SMC23 Data Out Valid before NWE High (nwe pulse length - 1) * tCPSMC - 0.
AT32UC3A Table 38-26. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol Parameter Min SMC37 NWE Rising to A2-A25 Valid 5.4 SMC38 NWE Rising to NBS0/A0 Valid 5 SMC39 NWE Rising to NBS1 Change 5 SMC40 NWE Rising to A1/NBS2 Change 5 SMC41 NWE Rising to NBS3 Change 5 SMC42 NWE Rising to NCS Rising SMC43 Data Out Valid before NWE Rising SMC44 Data Out Valid after NWE Rising SMC45 NWE Pulse Width Units ns 5.1 (nwe pulse length - 1) * tCPSMC - 1.
AT32UC3A Figure 38-3. SMC Signals for NRD and NRW Controlled Accesses. SMC37 SMC7 SMC7 SMC31 A2-A25 SMC25 SMC26 SMC29 SMC30 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 A0/A1/NBS[3:0] SMC42 SMC32 SMC8 NCS SMC8 SMC9 SMC9 NRD SMC19 SMC20 SMC43 SMC44 SMC1 SMC23 SMC2 SMC24 D0 - D15 SMC45 SMC33 NWE 38.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Table 38-27. SDRAM Clock Signal.
AT32UC3A Table 38-28. SDRAM Clock Signal. Symbol Parameter Min SDRAMC11 Address Change before SDCK Rising Edge 6.2 SDRAMC12 Address Change after SDCK Rising Edge 2.2 SDRAMC13 Bank Change before SDCK Rising Edge 6.3 SDRAMC14 Bank Change after SDCK Rising Edge 2.4 SDRAMC15 CAS Low before SDCK Rising Edge 7.4 SDRAMC16 CAS High after SDCK Rising Edge 1.9 SDRAMC17 DQM Change before SDCK Rising Edge 6.4 SDRAMC18 DQM Change after SDCK Rising Edge 2.
AT32UC3A Figure 38-4. SDRAMC Signals relative to SDCK.
AT32UC3A 38.10 JTAG Timings 38.10.1 JTAG Interface Signals Table 38-29.
AT32UC3A Figure 38-5. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Device Inputs Device Outputs JTAG9 JTAG10 38.11 SPI Characteristics Figure 38-6.
AT32UC3A Figure 38-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 38-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 38-9.
AT32UC3A Table 38-30. SPI Timings Symbol SPI0 Parameter MISO Setup time before SPCK rises (master) SPI1 MISO Hold time after SPCK rises (master) SPI2 SPCK rising to MOSI Delay (master) Conditions (1) 3.3V domain 3.3V domain (1) 3.3V domain (1) (1) SPI3 MISO Setup time before SPCK falls (master) 3.3V domain SPI4 MISO Hold time after SPCK falls (master) 3.3V domain (1) SPI5 SPCK falling to MOSI Delay (master) 3.
AT32UC3A Table 38-32. Ethernet MAC MII Specific Signals Symbol EMAC12 EMAC13 Parameter Conditions Hold for ERX from ERXCK Setup for ERXER from ERXCK Min (ns) Load: 20pF (1) 1.5 Load: 20pF (1) 1 (1) 0.5 EMAC14 Hold for ERXER from ERXCK Load: 20pF EMAC15 Setup for ERXDV from ERXCK Load: 20pF (1) 1.5 EMAC16 Hold for ERXDV from ERXCK Load: 20pF (1) 1 Note: Max (ns) 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Figure 38-10.
AT32UC3A Table 38-33. Ethernet MAC RMII Specific Signals Symbol Parameter Min (ns) Max (ns) EMAC21 ETXEN toggling from EREFCK rising 7 14.5 EMAC22 ETX toggling from EREFCK rising 7 14.7 EMAC23 Setup for ERX from EREFCK 1.5 EMAC24 Hold for ERX from EREFCK 0 EMAC25 Setup for ERXER from EREFCK 1.5 EMAC26 Hold for ERXER from EREFCK 0 EMAC27 Setup for ECRSDV from EREFCK 1.5 EMAC28 Hold for ECRSDV from EREFCK 0 Figure 38-11.
AT32UC3A Table 38-35.
AT32UC3A 39. Mechanical Characteristics 39.1 Thermal Considerations 39.1.1 Thermal Data Table 39-1 summarizes the thermal resistance data depending on the package. Table 39-1. 39.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP100 43.4 θJC Junction-to-case thermal resistance TQFP100 5.5 θJA Junction-to-ambient thermal resistance LQFP144 39.8 θJC Junction-to-case thermal resistance LQFP144 8.
AT32UC3A 39.2 Package Drawings Figure 39-1. TQFP-100 package drawing Table 39-2. Device and Package Maximum Weight 500 mg Table 39-3. Package Characteristics Moisture Sensitivity Level Table 39-4.
AT32UC3A Figure 39-2. LQFP-144 package drawing Table 39-5. Device and Package Maximum Weight 1300 Table 39-6. mg Package Characteristics Moisture Sensitivity Level Table 39-7.
AT32UC3A Figure 39-3. FFBGA-144 package drawing Table 39-8. Device and Package Maximum Weight 1300 Table 39-9. mg Package Characteristics Moisture Sensitivity Level MSL3 Table 39-10.
AT32UC3A 39.3 Soldering Profile Table 39-11 gives the recommended soldering profile from J-STD-20. Table 39-11. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec Preheat Temperature 175°C ±25°C Min. 150 °C, Max. 200 °C Time Maintained Above 217°C 60-150 sec Time within 5⋅C of Actual Peak Temperature 30 sec Peak Temperature Range 260 °C Ramp-down Rate 6 °C/sec Time 25⋅C to Peak Temperature Max.
AT32UC3A 40. Ordering Information Table 40-1. Ordering Information Device AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 40.
AT32UC3A 41. Errata All industrial parts labelled with -UES (engineering samples) are revision E parts. All automotive parts labelled with AT32UC3A0512-ALTRA or AT32UC3A0512-ALTTA are revision K parts. 41.1 Rev. K, L, M 41.1.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled.
AT32UC3A 3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4.
AT32UC3A For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 41.1.9 FLASHC 1. Reading from on-chip flash may fail after a flash fuse write operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands).
AT32UC3A 41.2 Rev. J 41.2.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
AT32UC3A When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4.
AT32UC3A None. 41.2.9 USART 41.2.10 1. ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12.
AT32UC3A 41.3 Rev. I 41.3.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
AT32UC3A When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4.
AT32UC3A Workaround/fix The same PID should not be assigned to more than one channel. 41.3.7 GPIO 1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant Only 11 GPIOs remain 5V tolerant (VIHmax=5V):PB01, PB02, PB03, PB10, PB19, PB20, PB21, PB22, PB23, PB27, PB28. Workaround/fix None. 41.3.8 USART 1. ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None. 41.3.9 TWI 1.
AT32UC3A specific case. 2. Execute the RETE instruction. 41.3.12 FLASHC 1. Reading from on-chip flash may fail after a flash fuse write operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands). After a flash fuse write operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands), the following flash read access may return corrupted data. This erratum does not affect write operations to regular flash memory.
AT32UC3A 41.4 Rev. H 41.4.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle.
AT32UC3A 4. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 5.
AT32UC3A (data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or through the EBI. After these commands, read twice one flash page initialized to 00h in each half part of the flash. 41.4.6 PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID.
AT32UC3A RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Woraround Workaround 1: Make system stack readable in unprivileged mode, or Workaround 2: Return from supervisor mode using rete instead of rets. This requires : 1. Changing the mode bits from 001b to 110b before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically.
AT32UC3A 41.5 Rev. E 41.5.1 SPI 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 3.
AT32UC3A Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 41.5.2 PWM 1. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 2.
AT32UC3A 41.5.4 USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared by the hardware at the end of the reset. Fix/Workaround A software workaround consists in testing (by polling or interrupt) the disconnection (UHINT.DDISCI == 1) while waiting for the end of reset (UHCON.RESET == 0) to avoid being stuck. 2.
AT32UC3A 6. CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision E does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, so when the CPU clock stops, so does incrementing of COUNT. Fix/Workaround None. 7. Memory Protection Unit (MPU) is non functional. Fix/Workaround Do not use the MPU. 8.
AT32UC3A 12. CPU cannot operate on a divided slow clock (internal RC oscillator) Fix/Workaround Do not run the CPU on a divided slow clock. 13. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 14.
AT32UC3A 2. USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard should be different from 0. 3. USART Handshaking: 2 characters sent / CTS rises when TX If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty, the TXHOLDING is also transmitted. Fix/Workaround None. 4.
AT32UC3A Fix/Workaround In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour. 4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz. Fix/Workaround Do not set PBA frequency higher than 33 MHz. 5. PCx pins go low in stop mode In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators. This can cause drive contention on the XINx in worst case. Fix/Workaround Before entering stop mode set all PCx pins to input and GPIO controlled.
AT32UC3A If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 41.5.11 ABDAC 1. Audio Bitstream DAC is not functional. Fix/Workaround Do not use the ABDAC on revE. 41.5.12 FLASHC 1. The address of Flash General Purpose Fuse Register Low (FGPFRLO) is 0xFFFE140C on revE instead of 0xFFFE1410. Fix/Workaround None. 2.
AT32UC3A 2. The RTC CLKEN bit (bit number 16) of CTRL register is not available. Fix/Workaround Do not use the CLKEN bit of the RTC on Rev E. 41.5.14 OCD 1. Stalled memory access instruction writeback fails if followed by a HW breakpoint. Consider the following assembly code sequence: A B If a hardware breakpoint is placed on instruction B, and instruction A is a memory access instruction, register file updates from instruction A can be discarded.
AT32UC3A 42. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 42.1 Rev. K – 01/12 42.2 42.3 42.4 42.5 1. Update Errata Section 2. Update Electrical characteristic Section 1. Remove ordering code for automotive engineering samples 2. Replace old automotive odering codes AT32UC3A0512-ALTR (revision I) by AT32UC3A0512-ALTRA (revision K).
AT32UC3A 42.6 Rev. E – 04/08 42.7 1. Open Drain Mode removed from ”General-Purpose Input/Output Controller (GPIO)” on page 151. 1. Updated ”Signal Description List” on page 8. Removed RXDN and TXDN from USART section. 2. Updated ”Errata” on page 779. Rev G replaced by rev H. 1. Updated ”Signal Description List” on page 8. Removed RXDN and TXDN from USART section. 2. Updated ”Errata” on page 779. Rev G replaced by rev H. 1. Updated ”Features” on page 1. 2.
AT32UC3A Table of Contents 1 Description . ............................................................................................. 3 2 Configuration Summary . ........................................................................ 4 3 Abbreviations . ......................................................................................... 4 4 Blockdiagram . ......................................................................................... 5 4.1Processor and architecture . ..............
AT32UC3A 12.3Interrupt Request Signal Map . ...............................................................................41 12.4Clock Connections . ................................................................................................43 12.5Nexus OCD AUX port connections . .......................................................................44 12.6PDC handshake signals . .......................................................................................44 12.
AT32UC3A 17 External Interrupts Controller (EIC) . .................................................. 105 17.1Features . .............................................................................................................105 17.2Description . ..........................................................................................................105 17.3Block Diagram . ....................................................................................................106 17.4Product Dependencies .
AT32UC3A 12.3Interrupt Request Signal Map ................................................................................41 12.4Clock Connections .................................................................................................43 12.5Nexus OCD AUX port connections ........................................................................44 12.6PDC handshake signals ........................................................................................44 12.
AT32UC3A 25.1Features . .............................................................................................................259 25.2Overview . .............................................................................................................259 25.3Block Diagram . ....................................................................................................260 25.4Application Block Diagram . ..................................................................................260 25.
AT32UC3A 29 Ethernet MAC (MACB) . ....................................................................... 437 29.1Features . .............................................................................................................437 29.2Description . ..........................................................................................................437 29.3Block Diagram . ....................................................................................................438 29.
AT32UC3A 33.2Overview . .............................................................................................................699 33.3Block Diagram . ....................................................................................................700 33.4I/O Lines Description . ..........................................................................................700 33.5Product Dependencies . .......................................................................................700 33.
AT32UC3A 38 Electrical Characteristics . .................................................................. 763 38.1Absolute Maximum Ratings* . ..............................................................................763 38.2DC Characteristics . ..............................................................................................764 38.3Regulator characteristics . ....................................................................................765 38.4Analog characteristics . ..............
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