Datasheet

2
Atmel AT27C040 [DATASHEET]
0189J–EPROM–10/2012
2. Pin Configurations and Pinouts
3. Switching Considerations
Switching between active and standby conditions via the Chip Enable (CE) pin may produce transient voltage
excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in
device nonconformance. At a minimum, a 0.1μF, high-frequency, low inherent inductance, ceramic capacitor should be
utilized for each device. This capacitor should be connected between the V
CC
and ground terminals of the device — as
close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7μF bulk electrolytic capacitor should be utilized, again connected between the V
CC
and ground
terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to
the array.
4. Block Diagram
Pin
Name
Function
V
PP
Peak to Peak Voltage
A
0
- A
18
Address Inputs
O
0
- O
7
Outputs
GND Ground
CE Chip Enable
OE Output Enable
V
CC
Device Power Supply
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
4 3 2 1
32 31 30
14 15 16 17 18 19 20
O
1
O
2
GND
O
3
O
4
O
5
O
6
A
12
A
15
A
16
V
PP
V
CC
A
18
A
17
32-lead PLCC
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
32-lead PDIP
Top view
V
CC
GND
V
PP
A
0
– A
18
Address
Inputs
OE
CE
OE, CE, and
Program Logic
Y Decoder
X Decoder
Data Outputs
O
0
– O
7
Output
Buffers
Y-Gating
Cell Matrix
Identification