Datasheet

2
0321N–EPROM–4/11
Atmel AT27C010
2. Pin configurations
s
3. System considerations
Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless
accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance.
At a minimum, a 0.1µF, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the V
CC
and ground terminals of the device, as close to the device as possible.
Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7µF bulk electrolytic
capacitor should be utilized, again connected between the V
CC
and ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
Figure 3-1. Block diagram
Pin name Function
A0 - A16 Addresses
O0 - O7 Outputs
CE Chip enable
OE Output enable
PGM Program strobe
NC No connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
O0
A14
A13
A8
A9
A11
OE
A10
CE
O7
4 3 2 1
32 31 30
14 15 16 17 18 19 20
O1 O2
GND
O3 O4 O5 O6
A12 A15 A16 VPP VCC PGM NC
32-lead PLCC
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
O7
O6
O5
O4
O3
32-lead PDIP
Top view