Datasheet

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS20001749K-page 8  2002-2013 Microchip Technology Inc.
2.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/
Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
V
CC must be 4.5V for proper operation of ERAL.
FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4: ERAL TIMING FOR 93C DEVICES
Note: After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
100 10x
•••
x
T
SV TCZ
Busy Ready
High-Z
T
EC
High-Z
VCC must be 4.5V for proper operation of ERAL.
CS
CLK
DI
DO
T
CSL
Check Status
100 10x
•••
x
T
SV TCZ
Busy Ready
High-Z
TEC
High-Z