Datasheet

 2002-2013 Microchip Technology Inc. DS20001749K-page 7
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4 Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93C’ devices where the
rising edge of CLK before the last address bit initiates
the write cycle.
The DO pin indicates the Ready/
Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2: ERASE TIMING FOR 93C DEVICES
Note: After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
11
1 A
N
AN-1 AN-2
•••
A0
T
SV
TCZ
Busy
Ready
High-Z
T
WC
High-Z
CS
CLK
DI
DO
T
CSL
Check Status
111A
N
AN-1 AN-2
•••
A0
T
SV TCZ
Busy Ready
High-Z
T
WC
High-Z