Datasheet

© 2005 Microchip Technology Inc. DS21822E-page 5
25AA256/25LC256
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17
16
16
17
19
18
don’t care
5
high-impedance
n + 2 n + 1 n n - 1
n
n + 2 n + 1 n
n
n - 1
CS
SCK
SI
SO
65
8
7
11
3
LSB in
MSB in
high-impedance
12
Mode 1,1
Mode 0,0
2
4
CS
SCK
SO
10
9
13
MSB out
ISB out
3
15
don’t care
SI
Mode 1,1
Mode 0,0
14