Datasheet

24AA64/24LC64/24FC64
DS21189T-page 4  1997-2012 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
13 TAA Output valid from clock
(Note 2)
—
—
—
—
3500
900
900
400
ns 1.7V  VCC  2.5V
2.5V  V
CC  5.5V
1.7V  V
CC  2.5V 24FC64
2.5V  V
CC  5.5V 24FC64
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
1300
500
—
—
—
—
ns 1.7V  VCC  2.5V
2.5V  V
CC  5.5V
1.7V  V
CC  2.5V 24FC64
2.5V  V
CC  5.5V 24FC64
15 T
OF Output fall time from VIH
minimum to VIL maximum
C
B  100 pF
10 + 0.1C
B 250
250
ns All except, 24FC64 (Note 1)
24FC64 (Note 1)
16 TSP Input filter spike suppression
(SDA and SCL pins)
— 50 ns All except, 24FC64 (Notes 1
and 3)
17 T
WC Write cycle time (byte or
page)
—5ms—
18 — Endurance 1,000,000 — cycles Page Mode 25°C, 5.5V (Note 4)
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): V
CC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): V
CC = +1.7V to 5.5V TA = -40°C to 125°C
Param.
No.
Sym. Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. C
B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D3
4
10
11
12
14