Datasheet

24AA1026/24LC1026/24FC1026

DS22270A-page 4  2011 Microchip Technology Inc.

FIGURE 1-1: BUS TIMING DATA

14 TBUF Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.8V  V

CC  2.5V (24FC1026 only)

2.5V  V

CC  5.5V (24FC1026 only)

15 T

SP Input filter spike suppression

(SDA and SCL pins)

— 50 ns All except 24FC1026 (Note 1 and Note 3)

16 T

WC Write cycle time (byte or page) — 5 ms —

17 Endurance 1,000,000 — cycles Page mode, 25°C, V

CC = 5.5V (Note 4)

AC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,

please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

(unprotected)

(protected)

SCL

SDA

OUT