User`s guide

MPLAB
®
IDE User’s Guide
DS51519B-page 218 © 2006 Microchip Technology Inc.
16.3.6.2 SYSTEM INTEGRATION BLOCK
Reset Sources
All Reset sources are supported by the MPLAB SIM simulator.
Status bits from the RCON register are set or cleared differently in different Reset
situations, as indicated in device data sheet. These bits are used in software to
determine the nature of the Reset.
A MCLR
Reset during normal operation or during Sleep/Idle can easily be simulated by
driving the MCLR
pin low (and then high) via stimulus or by selecting Debugger>
Reset>MCLR Reset.
Sleep/Idle
When executing a PWRSAV instruction, MPLAB SIM will appear “asleep” or “idle” until
a wake-up condition occurs. For example, if the Watchdog Timer has been enabled, it
will wake the processor up from sleep when it times out (depending upon the
pre/postscaler setting).
An example of a wake-up-from-sleep condition would be Timer1 wake up from sleep.
In this case, when the processor is asleep, Timer1 would continue to increment until it
matches the period counter. If the interrupt is enabled, the timer will wake the processor
and branch to the interrupt vector.
Watchdog Timer
The Watchdog Timer is fully simulated in the MPLAB SIM simulator.
The Watchdog Timer can be “Enabled” or “Disabled” through a Configuration bit
(FWDTEN) in the Configuration register FWDT. Setting FWDTEN = 1 enables the
Watchdog Timer. Setting FWDTEN = 0 allows user software to enable/ disable the
Watchdog Timer via the SWDTEN (RCON<5>) control bit.
The period of the WDT is determined by the pre/postscaler settings in the FWDT
register. The minimum period (with pre/postscaler at 1:1) may be set on the Break
Options tab of the Settings dialog (Debugger>Settings
).
In the Configuration Bits dialog (Configuration>Configuration Bits
) you enable/disable
the WDT and set the pre/postscalers.
A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and
WDT actually overflows. On WDT time-out, the simulator will halt or Reset, depending
on the selection in the Break Options tab of the Settings dialog.
16.3.6.3 MEMORY
PIC24/dsPIC DSC device memory – program flash and data RAM – is simulated except
for features dependent on security aspects. I.e., protected memory is not simulated.