User`s guide

MPLAB
®
IDE User’s Guide
DS51519B-page 216 © 2006 Microchip Technology Inc.
16.3.5.4 16-BIT CORE (PIC18) PERIPHERALS
Along with core support, MPLAB SIM supports the following peripheral modules, in
addition to general purpose I/O:
•Timers
• CCP/ECCP
• Comparators (Limited)
• A/D Converter (Limited)
•USART
• EEPROM Data Memory
The delays are implemented on all peripherals, but the interrupt latency is not.
Timers
Timer0 (and the interrupt it can generate on overflow) is fully supported, and will
increment by the internal or external clock. Clock input must have a minimum high time
of 1 T
CY and a minimum low time of 1 TCY due to stimulus requirements.
All Other Timers in their various modes are supported, except for modes using an
external crystal. MPLAB SIM supports Timer interrupts generated on overflow, and
interrupts generated by wake-up from sleep. Although the external oscillator is not
simulated, a clock stimulus can be assigned to those pins.
CCP/ECCP
Capture
MPLAB SIM fully supports capture and the interrupt generated.
Compare
MPLAB SIM supports compare mode, its interrupt and the special event trigger
(resetting a Timer by CCP).
PWM
PWM output is supported (resolution greater than 1 T
CY only).
Comparators (Limited)
Only comparator modes that do not use Vref are simulated in MPLAB SIM.
Because simulation is to the register level, and not the pin level, bit/pin names will be
read as ‘0’, as required for analog, although injected stimulus may have actually
changed the value to ‘1’.
Toggling a comparator pin will not work since toggling involves reading a value and
inverting it. Since the value always reads ‘0’, the bit/pin never toggles. Instead, use two
statements to toggle a comparator pin, e.g.,
• RA1 set low
• RA1 set high