User`s guide

MPLAB
®
IDE User’s Guide
DS51519B-page 214 © 2006 Microchip Technology Inc.
Timer0
Timer0 and the interrupt it can generate on overflow is fully supported, and will
increment by the internal or external clock. Delay from external clock edge to timer
increment has also been simulated, as well as the interrupt latency period. Clock input
must have a minimum high time of 1 T
CY and a minimum low time of 1 TCY due to the
stimulus file requirements.
Timer1 and Timer2
Timer1 and Timer2 in its various modes is fully supported. Delays from clock edge to
increment (when configured to increment from rising or falling edge of external clock)
is simulated as well as the interrupt latency periods. Clock input must have a minimum
high time of 1 T
CY and a minimum low time of 1 TCY due to the stimulus file
requirements.
Timer3 and Capture
The MPLAB simulator fully supports Timer3 and the Capture module in all of its modes.
Delays from clock edge to increment (when configured in external mode), delay for
capture and interrupt latency periods are fully supported. Clock input must have a
minimum high time of 1 T
CY and a minimum low time of 1 TCY due to the stimulus file
requirements.
PWM
Both PWM outputs are supported (resolution greater than 1 TCY only).
16.3.5 16-Bit Core Device Simulation – PIC18
The following topics discuss the enhanced 16-bit core device features modeled in the
simulator.
16-bit Core (PIC18) Interrupts
16-bit Core (PIC18) CPU
16-bit Core (PIC18) Processor Modes
16-bit Core (PIC18) Peripherals
16.3.5.1 16-BIT CORE (PIC18) INTERRUPTS
The following interrupts are supported:
External interrupt on INT pin
TMR0 overflow interrupt
External interrupt on RA0 pin
Port B input change interrupt
Timer/Counter1 interrupt
Timer/Counter2 interrupt
Timer/Counter3 interrupt
Capture1 interrupt
Capture2 Interrupt