User`s guide

Simulator Overview
© 2006 Microchip Technology Inc. DS51519B-page 213
16.3.4.2 16-BIT CORE (PIC17) CPU
Reset Conditions
All Reset conditions are supported by the MPLAB SIM simulator.
The Time out (TO) and Power-Down (PD) bits in the CPUSTA register reflect appropri-
ate Reset condition. This feature is useful for simulating various power-up and time-out
forks in the user code.
A MCLR
Reset during normal operation or during Sleep can easily be simulated by
driving the MCLR
pin low (and then high) via stimulus.
Sleep
When executing a Sleep instruction, MPLAB SIM will appear “asleep” until a wake-up
from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it
will wake the processor up from sleep when it times out (depending upon the postscaler
setting).
An example of a wake-up-from-sleep condition would be an input change on Port B. If
the interrupt is enabled and the GLINTD bit is set, the processor will wake up and will
resume executing from the instruction following the Sleep command. If the
GLINTD = 0, the normal interrupt response will take place.
Watchdog Timer
The Watchdog Timer is fully simulated in the MPLAB SIM simulator.
The period of the WDT is determined by the postscaler Configuration bits WDTPS0:1.
The minimum period (with postscaler at 1:1) is approximated, to the closest instruction
cycle multiple, to the value in the device data sheet. Setting the Configuration bits
WDTPS0:‘1’ to ‘00’ will disable the WDT.
In the Configuration Bits dialog (Configuration>Configuration Bits
) you enable/disable
the WDT and set the postscaler.
A WDT time-out is simulated when WDT is enabled, proper postscaler is set and WDT
actually overflows. On WDT time-out, the simulator will halt or Reset, depending on the
selection in the Break Options tab of the Settings dialog.
16.3.4.3 16-BIT CORE (PIC17) PROCESSOR MODES
The following processor modes are supported by MPLAB SIM for devices which allow
them:
• Microcontroller (Default)
• Extended Microcontroller
• Microprocessor
For information on external memory, see Section 17.6 “Using External Memory”.
16.3.4.4 16-BIT CORE (PIC17) PERIPHERALS
Along with providing core support, MPLAB SIM supports the following peripheral
modules, in addition to general purpose I/O:
•Timer0
• Timer1 and Timer2
• Timer3 and Capture
•PWM
The delays are implemented on all peripherals, but the interrupt latency is not.