User`s guide

MPLAB
®
IDE User’s Guide
DS51519B-page 212 © 2006 Microchip Technology Inc.
A/D Converter (Limited)
All the registers, timing function and interrupt generation are implemented. The
simulator, however, does not load any meaningful value into the A/D result register
(ADRES) at the end of a conversion.To load meaningful data, use an injection file (see
Section 18.2.5 “Register Injection”). A read of the A/D register will load this data into
the register.
Because simulation is to the register level, and not the pin level, bit/pin names will be
read as ‘0’, as required for analog, although injected stimulus may have actually
changed the value to ‘1’.
USART
USART functionality is supported. For more information, see Section 17.7 “Using a
USART/UART”.
EEPROM Data Memory
The EEPROM data memory is fully simulated. The registers and the read/write cycles
are fully implemented. The write cycle time is approximated to 10 ms (to nearest
instruction cycle multiple).
The simulator simulates the functions of WRERR and WREN control bits in the
EECON1 register.
16.3.4 16-Bit Core Device Simulation – PIC17
The following topics discuss the 16-bit core device features modeled in the simulator.
• 16-bit Core (PIC17) Interrupts
• 16-bit Core (PIC17) CPU
• 16-bit Core (PIC17) Processor Modes
• 16-bit Core (PIC17) Peripherals
16.3.4.1 16-BIT CORE (PIC17) INTERRUPTS
The following interrupts are supported:
• External interrupt on INT pin
• TMR0 overflow interrupt
• External interrupt on RA0 pin
• Port B input change interrupt
• Timer/Counter1 interrupt
• Timer/Counter2 interrupt
• Timer/Counter3 interrupt
• Capture1 interrupt
• Capture2 Interrupt
Note: If you have trouble with I/O pins on processors that have A/D, make certain
that the ADCON registers are configuring those pins for digital I/O rather
than for analog input. For most processors, these default to analog inputs
and the associated pins cannot be used for I/O until the ADCON (or
ADCON1) register is set properly.