User`s guide

MPLAB
®
IDE User’s Guide
DS51519B-page 210 © 2006 Microchip Technology Inc.
16.3.3 14-Bit Core Device Simulation
The following topics discuss the 14-bit core device features modeled in the simulator.
• 14-bit Core Interrupts
• 14-bit Core CPU
• 14-bit Core Peripherals
16.3.3.1 14-BIT CORE INTERRUPTS
The following interrupts are supported:
• Timer0 overflow
• Timer1 overflow
•Timer2
• CCP1
• CCP2
• Change on Port RB <7:4>
• External interrupt from RB0/INT pin
•Comparators
• A/D complete
• EEPROM write complete
16.3.3.2 14-BIT CORE CPU
Reset Conditions
All Reset conditions are supported by the MPLAB SIM simulator.
The Time-out (TO) and Power-down (PD) bits in the STATUS register reflect appropri-
ate Reset condition. This feature is useful for simulating various power-up and time-out
forks in the user code.
A MCLR
Reset during normal operation or during Sleep can easily be simulated by
driving the MCLR
pin low (and then high) via stimulus or by selecting Debugger>
Reset>MCLR Reset.
Sleep
When executing a Sleep instruction, MPLAB SIM will appear “asleep” until a wake-up
from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it
will wake the processor up from sleep when it times out (depending upon the
pre/postscaler setting).
An example of a wake-up-from-sleep condition would be Timer1 wake up from sleep.
In this case, when the processor is asleep, Timer1 would continue to increment until it
overflows. If the interrupt is enabled, the timer will wake the processor on overflow and
branch to the interrupt vector.
Watchdog Timer
The Watchdog Timer is fully simulated in the MPLAB SIM simulator.
The period of the WDT is determined by the pre/postscaler settings in the
OPTION_REG register. The minimum period (with pre/postscaler at 1:1) may be set on
the Break Options tab of the Settings dialog (Debugger>Settings
).
In the Configuration Bits dialog (Configuration>Configuration Bits
) you enable/disable
the WDT.