User`s guide

Simulator Overview
© 2006 Microchip Technology Inc. DS51519B-page 209
16.3.2 12-Bit Core Device Simulation
The following topics discuss the 12-bit core device features modeled in the simulator.
• 12-bit Core CPU
• 12-bit Core Peripherals
16.3.2.1 12-BIT CORE CPU
Reset Conditions
All Reset conditions are supported by the MPLAB SIM simulator.
The Time-out (TO) and Power-down (PD) bits in the STATUS register reflect appropri-
ate Reset condition. This feature is useful for simulating various power-up and time-out
forks in your code.
A MCLR
Reset during normal operation can easily be simulated by driving the MCLR
pin low (and then high) via stimulus or by selecting Debugger>Reset>MCLR Reset
.
Watchdog Timer
The Watchdog Timer is fully simulated in the MPLAB SIM simulator.
The period of the WDT is determined by the pre/postscaler settings in the
OPTION_REG register. The minimum period (with pre/postscaler at 1:1) may be set on
the Break Options tab of the Settings dialog (Debugger>Settings
).
In the Configuration Bits dialog (Configuration>Configuration Bits
) you enable/disable
the WDT.
A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and
WDT actually overflows. On WDT time-out, the simulator will halt or Reset, depending
on the selection in the Break Options tab of the Settings dialog.
16.3.2.2 12-BIT CORE PERIPHERALS
Along with core support, MPLAB SIM fully supports the TIMER0 timer/counter module
in both internal and external clock modes.
It is important to remember that, because MPLAB SIM executes on instruction cycle
boundaries, resolutions below 1 T
CY cannot be simulated.