User Manual

11. Application Reference Design
The ATWINC3400-MR210CA module application schematics for different supported host interfaces are
shown in this section.
11.1 Host Interface - SPI
Figure 11-1. ATWINC3400-MR210CA Reference Schematic
R5 0
R90
R3 0
R20
R8 0
TP2
R100
U1
ATWINC3400-MR210
I2C_SCL_M
J34
I2C_SDA_M
J35
RESETN
J7
NC1
J3
NC2
J4
NC3
J5
NC4
J6
GND5
J36
SDIO~_SPI_CFG
J2
GND1
J1
IRQN
J33
UART_TxD
J16
SPI_MOSI
J26
SPI_SSN
J25
SPI_MISO
J24
SPI_SCK
J23
UART_RxD
J17
VBAT
J18
CHIP_EN
J19
VDDIO
J12
GPIO3
J14
GPIO4
J15
GND3
J22
GND4
J28
BT_TXD
J8
BT_RXD
J9
BT_RTS
J10
BT_CTS
J11
GPIO17
J29
GPIO18
J30
GPIO19
J31
GND2
J13
GPIO7
J27
GPIO20
J32
GND_PAD
J49
RTC
J20
R6 0
R1
1M
R4 0
R7 0
TP1
SPI_SSN
SPI_MISO
SPI_SCK
SPI_MOSI
Reset_N
Chip_EN
UART_TxD
UART_RxD
GPIO_17
IRQN
VBAT
GPIO_4
GPIO_7
VDDIO
VDDIO
To host U ART output
To host U ART input
(General Purpose I/O)
To host SPI M as ter
R esis tors R 2 - R 14 are rec om m ended
as placeholders in case filtering
of noisy s ignals is required. T hey
also allow dis c onnecting of m odule
for debug purposes .
GPIO_3
GPIO_19
GPIO_20
GPIO_18
(T o host GPIO)
(T o host GPIO)
R12 0
R11 0
BT_RTS
BT_CTS
To Hos t Input
To Hos t Output
BT_TxD
BT_RxD
To Hos t Input
To Hos t Output
R14 0
R13 0
C1
0.1uF
U2
32.768KHz
OE
3
VSS
2
O
1
VDD
4
VDDIO
Note: It is recommended to add test points for module pins J8, J9, J10, J11, J16 and J17 in the design.
The following table provides the reference Bill of Material (BoM) details for the ATWINC3400-MR210CA
module with SPI as host interface.
Table 11-1. ATWINC3400-MR210CA Reference Bill of Materials for SPI Operation
Item Quantity Referen
ce
Value Description Manufacturer Part
Number
Footprint
1 1 U1 ATWINC3400-
MR210CA
Wi-Fi/
Bluetooth/BLE
Microchip
Technology
Inc.
®
ATWINC340
0-MR210CA
Custom
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 35