User Manual
Table Of Contents
- Introduction
- Features
- Table of Contents
- 1. Ordering Information and Module Marking
- 2. Block Diagram
- 3. Pinout and Package Information
- 4. Electrical Characteristics
- 5. Power Management
- 6. Clocking
- 7. CPU and Memory Subsystem
- 8. WLAN Subsystem
- 9. Bluetooth Low Energy 4.0
- 10. External Interfaces
- 11. Application Reference Design
- 12. Module Outline Drawings
- 13. Design Consideration
- 14. Reflow Profile Information
- 15. Module Assembly Considerations
- 16. Regulatory Approval
- 17. Reference Documentation
- 18. Document Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Microchip Devices Code Protection Feature
- Legal Notice
- Trademarks
- Quality Management System Certified by DNV
- Worldwide Sales and Service
Parameter Symbol Min. Max. Units
RXD Input Setup Time t
ISU
1 —
RXD Input Hold Time t
IHD
5 —
SSN Input Setup Time t
SUSSN
3 —
SSN Input Hold Time t
HDSSN
5.5 —
Note:
1. Timing is applicable to all SPI modes
2. Maximum clock frequency specified is limited by the SPI Slave interface internal design, actual
maximum clock frequency can be lower and depends on the specific PCB layout
3. Timing based on 15pF output loading
10.3 UART Interface
The ATWINC3400-MR210CA supports the Universal Asynchronous Receiver/Transmitter (UART)
interface. This interface should be used for debug purposes only. The UART is available on pins 14 and
19. The UART is compatible with the RS-232 standard, and the ATWINC3400-MR210CA operates as
Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface.
The default configuration for accessing the UART interface of ATWINC3400-MR210CA is mentioned
below:
• Baud rate: 115200
• Data: 8 bit
• Parity: None
• Stop bit: 1 bit
• Flow control: None
It also has RX and TX FIFOs, which ensure reliable high-speed reception and low software overhead
transmission. FIFO size is 4 x 8 for both RX and TX direction. The UART also has status registers
showing the number of received characters available in the FIFO and various error conditions, as well the
ability to generate interrupts based on these status bits.
An example of the UART receiving or transmitting a single packet is shown in the following figure. This
example shows 7-bit data (0x45), odd parity, and two stop bits.
Important: UART2 supports RTS and CTS flow control. The UART RTS and UART CTS
MUST be connected to the host MCU UART and enabled for the UART interface to be
functional.
Figure 10-4. Example of UART RX of TX Packet
Previous
Packets or
Leading
Idle Bits
Current Packet
Data
Start
Bit
Parity
Bit
Stop Bits
Next
Packet
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 34