User Manual

Figure 10-2. SPI Slave Clock Polarity and Clock Phase Timing
z
z z
z
SCK
CPOL = 0
CPOL = 1
SSN
RXD/TXD
(MOSI/MISO)
CPHA = 0
CPHA = 1
2 3 4 5 6 7 8
1 2 3 4 5 6 7
1
8
The SPI timing is provided in the following figure and table.
Figure 10-3. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)
t
LH
SCK
TXD
RXD
t
WH
t
HL
t
WL
t
ODLY
t
ISU
t
IHD
f
SCK
SSN
t
SUSSN
t
HDSSN
Table 10-4. SPI Slave Timing Parameters
1
Parameter Symbol Min. Max. Units
Clock Input Frequency
2
f
SCK
— 48 MHz
Clock Low Pulse Width t
WL
4 —
ns
Clock High Pulse Width t
WH
5 —
Clock Rise Time t
LH
0 7
Clock Fall Time t
HL
0 7
TXD Output Delay
3
t
ODLY
4 9 from SCK fall
12.5 from SCK
rise
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 33