User Manual

10.2 SPI Interface
10.2.1 Overview
The ATWINC3400-MR210CA has a Serial Peripheral Interface (SPI) that operates as an SPI slave. The
SPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as
shown in the following table. The SPI is a full-duplex slave-synchronous serial interface that is available
immediately following reset when pin 10 (SPI_CFG) is tied to VDDIO.
Table 10-2. SPI Interface Pin Mapping
Pin # SPI function
10 CFG: Must be tied to VDDIO
16 SSN: Active Low Slave Select
15 MOSI(RXD): Serial Data Receive
18 SCK: Serial Clock
17 MISO(TXD): Serial Data Transmit
When the SPI is not selected, that is, when SSN is high, the SPI interface will not interfere with data
transfers between the serial-master and other serial-slave devices. When the serial slave is not selected,
its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the
chip as well as initiate DMA transfers.
The SPI SSN, MOSI, MISO, and SCK pins of the ATWINC3400-MR210CA have internal programmable
pull-up resistors. These resistors should be programmed to be disabled. Otherwise, if any of the SPI pins
are driven to a low level while the ATWINC3400-MR210CA is in the low-power sleep state, the current will
flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the
module.
10.2.2 SPI Timing
The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and
Clock Phase (CPHA) settings. These modes are illustrated in the following table and figure.
Table 10-3. SPI Slave Modes
Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1
The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to Clock
Phase = 1.
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 32