User Manual
Table Of Contents
- Introduction
- Features
- Table of Contents
- 1. Ordering Information and Module Marking
- 2. Block Diagram
- 3. Pinout and Package Information
- 4. Electrical Characteristics
- 5. Power Management
- 6. Clocking
- 7. CPU and Memory Subsystem
- 8. WLAN Subsystem
- 9. Bluetooth Low Energy 4.0
- 10. External Interfaces
- 11. Application Reference Design
- 12. Module Outline Drawings
- 13. Design Consideration
- 14. Reflow Profile Information
- 15. Module Assembly Considerations
- 16. Regulatory Approval
- 17. Reference Documentation
- 18. Document Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Microchip Devices Code Protection Feature
- Legal Notice
- Trademarks
- Quality Management System Certified by DNV
- Worldwide Sales and Service
8. WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC), Physical Layer (PHY), and
the radio.
8.1 MAC
The ATWINC3400-MR210CA module is designed to operate at low power, while providing high data
throughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath
engines, hardwired control logic, and a low power, high-efficiency microprocessor. The combination of
dedicated logic with a programmable processor provides optimal power efficiency and real time response
while providing the flexibility to accommodate evolving standards and future feature enhancements.
The dedicated datapath engines are used to implement datapath functions with heavy computational
requirements. For example, a Frame Check Sequence (FCS) engine checks the Cyclic Redundancy
Check (CRC) of the transmitting and receiving packets, and a cipher engine performs all the required
encryption and decryption operations for the WEP, WPA-TKIP, and WPA2 CCMP-AES security
requirements.
Control functions, which have real time requirements, are implemented using hardwired control logic
modules. These logic modules offer real time response while maintaining configurability through the
processor. Examples of hardwired control logic modules are the channel access control module
(implements EDCA/HCCA, Beacon Tx control, interframe spacing, and so on), protocol timer module
(responsible for the Network Access vector, back-off timing, timing synchronization function, and slot
management), MAC Protocol Data Unit (MPDU) handling module, aggregation/deaggregation module,
block ACK controller (implements the protocol requirements for burst block communication), and Tx/Rx
control Finite State Machine (FSM) (coordinates data movement between PHY and MAC interface, cipher
engine, and the Direct Memory Access (DMA) interface to the Tx/Rx FIFOs).
The following are the characteristics of MAC functions implemented solely in software on the
microprocessor:
• Functions with high memory requirements or complex data structures. Examples include
association table management and power save queuing.
• Functions with low computational load or without critical real time requirements. Examples include
authentication and association.
• Functions that require flexibility and upgradeability. Examples include beacon frame processing and
QoS scheduling.
Features
The ATWINC3400-MR210CA MAC supports the following functions:
• IEEE 802.11b/g/n
• IEEE 802.11e WMM QoS EDCA/HCCA/PCF multiple access categories traffic scheduling
• Advanced IEEE 802.11n features:
– Transmission and reception of aggregated MPDUs (A-MPDU)
– Transmission and reception of aggregated MSDUs (A-MSDU)
– Immediate block acknowledgment
– Reduced Interframe Spacing (RIFS)
• IEEE 802.11i and WFA security with key management:
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 27