User Manual
Table Of Contents
- Introduction
- Features
- Table of Contents
- 1. Ordering Information and Module Marking
- 2. Block Diagram
- 3. Pinout and Package Information
- 4. Electrical Characteristics
- 5. Power Management
- 6. Clocking
- 7. CPU and Memory Subsystem
- 8. WLAN Subsystem
- 9. Bluetooth Low Energy 4.0
- 10. External Interfaces
- 11. Application Reference Design
- 12. Module Outline Drawings
- 13. Design Consideration
- 14. Reflow Profile Information
- 15. Module Assembly Considerations
- 16. Regulatory Approval
- 17. Reference Documentation
- 18. Document Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Microchip Devices Code Protection Feature
- Legal Notice
- Trademarks
- Quality Management System Certified by DNV
- Worldwide Sales and Service
7. CPU and Memory Subsystem
7.1 Processor
The ATWINC3400-MR210CA module has two Cortus APS3 32-bit processors, one is used for Wi-Fi and
the other is used for Bluetooth. In IEEE 802.11 mode, the processor performs many of the MAC functions,
including but not limited to: association, authentication, power management, security key management,
and MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of
operation, such as Station (STA) and Access Point (AP) modes. In Bluetooth mode, the processor
handles multiple tasks of the Bluetooth protocol stack.
7.2 Memory Subsystem
The APS3 core uses a 256 KB instruction/boot ROM (160 KB for IEEE 802.11 and 96 KB for Bluetooth)
along with a 420 KB instruction RAM (128 KB for IEEE 802.11 and 292 KB for Bluetooth), and a 128 KB
data RAM (64 KB for IEEE 802.11 and 64 KB for Bluetooth). In addition, the device uses a 160 KB
shared/exchange RAM (128 KB for IEEE 802.11 and 32 KB for Bluetooth), accessible by the processor
and MAC, which allows the processor to perform various data management tasks on the Tx and Rx data
packets.
7.3 Nonvolatile Memory
The ATWINC3400-MR210CA module has 768 bits of nonvolatile eFuse memory that can be read by the
CPU after device reset. This nonvolatile One-Time-Programmable (OTP) memory can be used to store
customer-specific parameters, such as 802.11 MAC address and Bluetooth address; various calibration
information such as Tx power, crystal frequency offset, and other software-specific configuration
parameters. The eFuse is partitioned into six 128-bit banks. The bit map of the first and last banks is
shown in the following figure. The purpose of the first 80 bits in bank 0 and the first 56 bits in bank 5 is
fixed, and the remaining bits are general-purpose software dependent bits, reserved for future use.
Currently, the Bluetooth address is derived from the Wi-Fi MAC address (BT_ADDR=MAC_ADDR+1).
This eliminates the need to program the first 56 bits in bank 5. Since each bank and each bit can be
programmed independently, this allows for several updates of the device parameters following the initial
programming. For example, if the MAC address has to be changed, Bank 1 has to be programmed with
the new MAC address along with the values of Tx gain correction and frequency offset if they are used
and programmed in the Bank 0. The contents of Bank 0 have to be invalidated in this case by
programming the Invalid bit in the Bank 0. This will allow the firmware to use the MAC address from Bank
1.
By default, ATWINC3400-MR210CA modules are programmed with the MAC address and the frequency
offset bits of Bank 0.
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 25