User Manual

Table 5-2. Power-Up/Down Sequence Timing
Paramet
er
Min. Max.
Unit
s
Description Notes
t
A
0 - ms VBAT rise to
VDDIO rise
VBAT and VDDIO can rise simultaneously or
connected together. VDDIO must not rise before
VBAT.
t
B
0 - ms VDDIO rise to
CHIP_EN rise
CHIP_EN must not rise before VDDIO. CHIP_EN
must be driven high or low and must not be left
floating.
t
C
5 - ms CHIP_EN rise to
RESETN rise
This delay is required to stabilize the XO clock
before RESETN removal. RESETN must be driven
high or low and must not be left floating.
t
A’
0 - ms VDDIO fall to
VBAT fall
VBAT and VDDIO fall simultaneously or connected
together. VBAT must not fall before VDDIO.
t
B’
0 - ms CHIP_EN fall to
VDDIO fall
VDDIO must not fall before CHIP_EN. CHIP_EN
and RESETN must fall simultaneously.
t
C’
0 - ms RESETN fall to
VDDIO fall
VDDIO must not fall before RESETN. RESETN
and CHIP_EN fall simultaneously.
5.4 Digital I/O Pin Behavior During Power-Up Sequences
The following table represents the digital I/O pin states corresponding to the device power modes.
Table 5-3. Digital I/O Pin Behavior in Different Device States
Device State VDDIO
CHIP_E
N
RESET
N
Output Driver
Input
Driver
Pull Up/Down
Resistor (96
kOhm)
Power_Down: core supply
OFF
High Low Low Disabled (Hi-Z) Disabled Disabled
Power-On Reset: core
supply and hard reset ON
High High Low Disabled (Hi-Z) Disabled Enabled
Power-On Default: core
supply ON, device out of
reset and not programmed
High High High Disabled (Hi-Z) Enabled Enabled
On_Doze/ On_Transmit/
On_Receive: core supply
ON, device programmed by
firmware
High High High Programmed
by firmware for
each pin:
enabled or
disabled
Opposite
of
Output
Driver
state
Programmed by
firmware for
each pin:
enabled or
disabled
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 23