User Manual

Parameter Symbol Min. Max. Unit
SSN Input Setup Time t
SUSSN
5 -
SSN Input Hold Time t
HDSSN
5 -
Note:
1. Timing is applicable to all SPI modes.
2. Maximum clock frequency specified is limited by the SPI Slave interface internal design; actual
maximum clock frequency can be lower and depends on the specific PCB layout.
3. Timing based on 15 pF output loading.
4.6.3 SPI Master Timing
The SPI Master timing for the ATWINC3400-MR210CA module is shown in the following figure.
Figure 4-4. SPI Master Timing Diagram
The following table provides the SPI Master timing parameters for the ATWINC3400-MR210CA module .
Table 4-10. SPI Master Timing Parameters
(1)
Parameter Symbol Min. Max. Unit
Clock Output Frequency
(2)
f
SCK
- 20 MHz
Clock Low Pulse Width t
WL
19 - ns
Clock High Pulse Width t
WH
21 -
Clock Rise Time
(3)
t
LH
- 11
Clock Fall Time
(3)
t
HL
- 10
RXD Input Setup Time t
ISU
24 -
RXD Input Hold Time t
IHD
0 -
SSN/TXD Output Delay
(3)
t
ODLY
-5 3
Note:
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 19