User Manual

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Table Of Contents

Introduction
Features
Table of Contents
1. Ordering Information and Module Marking
2. Block Diagram
3. Pinout and Package Information
- 3.1. Package Description
4. Electrical Characteristics
- 4.1. Absolute Maximum Ratings
- 4.2. Recommended Operating Conditions
- 4.3. DC Characteristics
- 4.4. IEEE 802.11 b/g/n Radio Performance
  - 4.4.1. Receiver Performance
  - 4.4.2. Transmitter Performance
- 4.5. Bluetooth Radio Performance
  - 4.5.1. Receiver Performance
  - 4.5.2. Transmitter Performance
- 4.6. Timing Characteristics
5. Power Management
- 5.1. Device States
- 5.2. Controlling Device States
- 5.3. Power-Up/Down Sequence
- 5.4. Digital I/O Pin Behavior During Power-Up Sequences
6. Clocking
- 6.1. Low-Power Clock
7. CPU and Memory Subsystem
- 7.1. Processor
- 7.2. Memory Subsystem
- 7.3. Nonvolatile Memory
8. WLAN Subsystem
- 8.1. MAC
- 8.2. PHY
- 8.3. Radio
9. Bluetooth Low Energy 4.0
10. External Interfaces
- 10.1. Interfacing with the Host Microcontroller
- 10.2. SPI Interface
  - 10.2.1. Overview
  - 10.2.2. SPI Timing
- 10.3. UART Interface
11. Application Reference Design
- 11.1. Host Interface - SPI
12. Module Outline Drawings
13. Design Consideration
- 13.1. Module Placement and Routing Guidelines
- 13.2. Antenna Performance
14. Reflow Profile Information
- 14.1. Storage Condition
  - 14.1.1. Moisture Barrier Bag Before Opening
  - 14.1.2. Moisture Barrier Bag Open
- 14.2. Solder Paste
- 14.3. Stencil Design
- 14.4. Baking Conditions
- 14.5. Soldering and Reflow Condition
  - 14.5.1. Reflow Oven
15. Module Assembly Considerations
16. Regulatory Approval
- 16.1. United States
- 16.2. Canada
- 16.3. Europe
- 16.4. Other Regulatory Information
17. Reference Documentation
18. Document Revision History
The Microchip Web Site
Customer Change Notification Service
Customer Support
Product Identification System
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System Certified by DNV
Worldwide Sales and Service

Parameter Symbol Min. Max. Units Remarks

40 - µs

Master Programming

Option

STOP Setup Time t

SUSTO

0.6 -

µs

Bus Free Time Between

STOP and START

BUF

1.3 - -

Glitch Pulse Reject t

0 50 ns -

4.6.2 SPI Slave Timing

The SPI Slave timing for the ATWINC3400-MR210CA module is provided in the following figures.

Figure 4-2. SPI Slave Clock Polarity and Clock Phase Timing

ATWINC3400-MR210CA

Draft Datasheet Preliminary

DS00000000A-page 17