User Manual
Table Of Contents
- Introduction
- Features
- Table of Contents
- 1. Ordering Information and Module Marking
- 2. Block Diagram
- 3. Pinout and Package Information
- 4. Electrical Characteristics
- 5. Power Management
- 6. Clocking
- 7. CPU and Memory Subsystem
- 8. WLAN Subsystem
- 9. Bluetooth Low Energy 4.0
- 10. External Interfaces
- 11. Application Reference Design
- 12. Module Outline Drawings
- 13. Design Consideration
- 14. Reflow Profile Information
- 15. Module Assembly Considerations
- 16. Regulatory Approval
- 17. Reference Documentation
- 18. Document Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Microchip Devices Code Protection Feature
- Legal Notice
- Trademarks
- Quality Management System Certified by DNV
- Worldwide Sales and Service
Parameter Description Min. Typ. Max. Unit
In-band spurious
emission (Bluetooth Low
Energy)
N+2 (Image frequency) - -33 -
N + 3 (Adjacent to image
frequency)
- -32 -
N-2 - -50 -
N-3 - -49 -
4.6 Timing Characteristics
4.6.1 I
2
C Slave Timing
The I
2
C Slave timing diagram for the ATWINC3400-MR210CA module is shown in the following figure.
Figure 4-1. I
2
C Slave Timing Diagram
The following table provides the I
2
C Slave timing parameters for the ATWINC3400-MR210CA module.
Table 4-8. I
2
C Slave Timing Parameters
Parameter Symbol Min. Max. Units Remarks
SCL Clock Frequency f
SCL
0 400 kHz -
SCL Low Pulse Width t
WL
1.3 -
µs
-
SCL High Pulse Width t
WH
0.6 - -
SCL, SDA Fall Time t
HL
- 300
ns
-
SCL, SDA Rise Time t
LH
- 300
This is dictated by
external components
START Setup Time t
SUSTA
0.6 -
µs
-
START Hold Time t
HDSTA
0.6 - -
SDA Setup Time t
SUDAT
100 - ns -
SDA Hold Time t
HDDAT
0 - ns Slave and Master Default
ATWINC3400-MR210CA
© 2017 Microchip Technology Inc.
Draft Datasheet Preliminary
DS00000000A-page 16