Datasheet

High-Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
Datasheet
Revision 1.3 (03-13-13) 22 SMSC USB4640/USB4640i
DATASHEET
The SPI_SPD_SEL pin is used to choose the speed of the SPI interface. During nRESET assertion,
this pin will be tri-stated with the weak pull-down resistor enabled. When nRESET is negated, the value
on the pin will be internally latched, and the pin will revert to SPI_DO functionality. The internal pull-
down will be disabled.
The firmware can determine the speed of operation on the SPI port by checking the
SPI_CTL.SPI_SPEED bit (0x2400 - RESET = 0x02). Both 1- and 2-bit SPI operation is supported. For
optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMS are also
supported.
Figure 3.5 SPI ROM Connection
Figure 3.6 I
2
C Connection
3.7 Pin Reset States
Figure 3.7 Pin Reset States
SPI ROM
SPI_CE_N
SPI_CLK/GPIO4/SCL
SPI_DI
SPI_DO/GPIO5/SDA/SPI_SPD_SEL
CE#
CLK
SI
SO
USB4640/40i
I
2
C ROM
SCL
SDA
3. 3 V
3. 3 V
10 K
10 K
USB4640/40i
Voltage
Signal
(v)
Time
(t)
RESET
RESET
Hardware
Initialization
Firmware
Operational
V
DD33
V
SS