Datasheet

High-Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
Datasheet
SMSC USB4640/USB4640i 21 Revision 1.3 (03-13-13)
DATASHEET
Schmitt trigger input will register this as a low resulting in an over-current detection. The open drain
output does not interfere.
Figure 3.3 Port Power Control with a Single Poly Fuse and Multiple Loads
When using a single poly fuse to power all devices, note that for the ganged situation, all power control
pins must be tied together.
Figure 3.4 Port Power with Ganged Control with Poly Fuse
3.6 ROM BOOT Sequence
After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid
signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is
found, then the external ROM is enabled and code execution begins at address 0x0000 in the external
SPI device. Otherwise, code execution continues from the internal ROM.
If there is no SPI ROM detected, the internal firmware then checks for the presence of an I
2
C ROM.
The firmware looks for the signature ATA2 at the offset of FCh-FFh and ecf1 at the offset of 17Ch-
17Fh in the I
2
C ROM. The firmware reads in the I
2
C ROM to configure the hardware and software
internally. Please refer to Section 4.3.2: EEPROM Data Descriptor on page 26 for the details of the
configuration options.
The SPI ROM required for the USB4640/USB4640i is a recommended minimum of 1 Mb and support
either 30 MHz or 60 MHz. The frequency used is set using the SPI_SPD_SEL. For 30 MHz operation,
this pin must be pulled to ground through a 100 kΩ resistor. For 60 MHz operation, this pin must pulled
up through a 100 kΩ resistor.
USB4640/40i
USB
Device
5 V
PRTCTL3
USB
Device
5V
PRTCTL2
USB
Device
Poly Fuse
5 V
USB
Device
PRTCTL2
PRTCTL3
USB4640/40i