Datasheet

High-Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
Datasheet
Revision 1.3 (03-13-13) 18 SMSC USB4640/USB4640i
DATASHEET
3.4 Buffer Type Descriptions
nRESET 38 IS Reset Input
The system uses this active low signal to reset the chip. The active
low pulse should be at least 1 μs wide.
TEST 40 I Test Input
Tie to ground for normal operation.
DIGITAL / POWER / GROUND
CRFILT 15 VDD Core Regulator Filter Capacitor
Requires a 1.0 μF (or greater) ± 20% (ESR <0.1
Ω) capacitor to VSS.
PLLFILT 46 Phase-Locked Loop Regulator Filter Capacitor
Requires a 1.0 μF (or greater) ± 20% (ESR < 0.1
Ω) capacitor to
VSS.
VDD12 41 1.2 V Power
For HSIC pads and buffers
VDD33 5
12
16
25
34
48
3.3 V Power and Regulator Input
See Chapter 6: DC Parameters on page 51 for more information.
Pins 16 and 48 each require an external bypass capacitor of 4.7 μF
minimum.
VSS ePad Ground Pad/ePad
The package slug is the only VSS for the device and must be tied to
ground with multiple vias.
Table 3.3 USB4640/USB4640i Buffer Type Descriptions
BUFFER DESCRIPTION
I Input.
I/O Input/output
IPU Input with weak internal pull-up
IS Input with Schmitt trigger
I/O6 Input/output buffer with 6 mA sink and 6 mA source
I/OD6PU Input/open drain output buffer with a 6 mA sink
O8 Output buffer with an 8 mA sink and an 8 mA source
O8PD Output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-down resistor
O8PU Output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-up resistor
I/O8 Input/output buffer with an 8 mA sink and an 8 mA source
Table 3.2 USB4640/USB4640i Pin Descriptions (continued)
SYMBOL
48-PIN
QFN
BUFFER
TYPE DESCRIPTION