Datasheet

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Revision 1.0 (07-14-09) 76 SMSC USB3320
DATASHEET
8.2 Reference Designs
SMSC has generated reference designs for connecting the USB3320 to SOCs with a ULPI port. Please
contact the SMSC sales office for more details.
8.3 ESD Performance
The USB3320 is protected from ESD strikes. By eliminating the requirement for external ESD
protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost.
The advanced ESD structures integrated into the USB3320 protect the device whether or not it is
powered up.
Figure 8.3 USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
VBUS
Switch
OUT
EN
IN
5V
VBUS
22
VBAT
21
VDD33
20
ID
23
DM
DP
19
18
SPK_L
SPK_R
16
15
GND
Optional
Switched Signal
to DP/DM
USB
Receptacle
DM
DP
ID
SHIELD
GND
VBUS
C
OUT
3.1-5.5V
Supply
C
BYP
R
VBUS
The capacitor C
VBUS
must be installed on
this side of R
VBUS
.
C
VBUS
R
VBUS
must be
installed to enable
overvoltage
protection of the
VBUS pin.
REFSEL2
14
REFSEL1
11
REFSEL0
8
VDDIO Supply
CPEN
17
Link Controller
DIR
NXT
STP
CLKIN
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
R
BIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
13
10
9
7
6
5
4
3
29
2
31
1
RESETB
27
24
RBIAS
VDD18
28, 30
1.8V Supply
C
BYP
VDDIO
C
BYP
VDDIO Supply
32
26
25
1MΩ
C
LOAD
Resonator
Crystal
and Caps
- or -
REFCLK
XO
For Host applications (non-OTG), the
ID pin should be connected to GND.