Datasheet

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Revision 1.0 (07-14-09) 66 SMSC USB3320
DATASHEET
7.1.1.10 USB Interrupt Status
Address = 13h (read only)
This register dynamically updates to reflect current status of interrupt sources.
Note: The default conditions will match the current status of the comparators. The values shown are
for an unattached OTG device.
7.1.1.11 USB Interrupt Latch
Address = 14h (read only with auto clear)
Note 7.2 rd: Read Only with auto clear.
Reserved 7:5 rd 000b Read only, 0.
FIELD NAME BIT ACCESS DEFAULT DESCRIPTION
HostDisconnect 0
rd
0b Current value of the UTMI+ Hi-Speed Hostdisconnect
output. Applicable only in host mode.
VbusValid 1 rd 0b Current value of the UTMI+ Vbusvalid output.
SessValid 2 rd 0b Current value of the UTMI+ SessValid output.
SessEnd 3 rd 0b Current value of the UTMI+ SessEnd output.
IdGnd 4 rd 0b Current value of the UTMI+ IdGnd output.
Reserved 7:5 rd 000b Read only, 0.
FIELD NAME BIT ACCESS DEFAULT DESCRIPTION
HostDisconnect Latch 0
rd
(Note 7.2)
0b Set to 1b by the transceiver when an unmasked
event occurs on Hostdisconnect. Cleared when this
register is read. Applicable only in host mode.
VbusValid Latch 1
rd
(Note 7.2)
0b Set to 1b by the transceiver when an unmasked
event occurs on VbusValid. Cleared when this
register is read.
SessValid Latch 2
rd
(Note 7.2)
0b Set to 1b by the transceiver when an unmasked
event occurs on SessValid. Cleared when this
register is read.
SessEnd Latch 3
rd
(Note 7.2)
0b Set to 1b by the transceiver when an unmasked
event occurs on SessEnd. Cleared when this register
is read.
IdGnd Latch 4
rd
(Note 7.2)
0b Set to 1b by the transceiver when an unmasked
event occurs on IdGnd. Cleared when this register is
read.
Reserved 7:5 rd 000b Read only, 0.
FIELD NAME BIT ACCESS DEFAULT DESCRIPTION