Datasheet

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Revision 1.0 (07-14-09) 10 SMSC USB3320
DATASHEET
Chapter 2 USB3320 Pin Locations and Definitions
2.1 USB3320 Pin Locations and Descriptions
2.1.1 Package Diagram with Pin Locations
The illustration below is viewed from the top of the package.
2.1.2 Pin Definitions
The following table details the pin definitions for the figure above.
Figure 2.1 USB3320 Pin Locations - Top View
Table 2.1 USB3320 Pin Description
PIN NAME
DIRECTION/
TYPE
ACTIVE
LEVEL DESCRIPTION
1CLKOUT
Output,
CMOS
N/A ULPI Output Clock Mode:
60MHz ULPI clock output. All ULPI
signals are driven synchronous to the
rising edge of this clock.
ULPI Input Clock Mode:
This pin is connected to VDDIO to
configure 60MHz ULPI Input Clock mode
as described in Section 5.4.1.
Following POR or hardware reset, the
voltage at CLKOUT must not exceed
V
IH_ED
as provided inTa b le 4. 4 .
CLKOUT
NXT
DATA0
DATA1
DATA2
DATA3
REFSEL0
DATA4
DATA5 DATA6
REFSEL1
N/C
DATA7
REFSEL2
SPK_R
SPK_L
RBIAS
CPEN
DM
DP
VBUS
VBAT
VDD33
ID
VDDIO
XO
RESETB REFCLK VDD18 STP VDD18 DIR
USB3300
Hi-Speed USB2
ULPI PHY
32 Pin QFN
1
2
3
4
5
6
7
8
Hi-Speed USB
ULPI PHY
32 Pin QFN
GND FLAG
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25