Datasheet

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SMSC USB3320 Revision 1.0 (07-14-09)

DATASHEET

Datasheet

PRODUCT FEATURES

USB3320

Highly Integrated Full Featured

Hi-Speed USB 2.0 ULPI

Transceiver

 Integrated ESD protection circuits

— Up to ±15kV IEC Air Discharge without external

devices

 Over-Voltage Protection circuit (OVP) protects the

VBUS pin from continuous DC voltages up to 30V

 Integrated USB Switch

— No degradation of Hi-Speed electrical

characteristics

— Allows single USB port of connection by

providing switching function for:

– Battery charging

– Stereo and mono/mic audio

– USB Full-Speed/Low-Speed data

 flexPWR

Technology

— Low current design ideal for battery powered

applications

— “Sleep” mode tri-states all ULPI pins and places

the part in a low current state

— 1.8V to 3.3V IO Voltage (±10%)

 Integrated battery to 3.3V regulator

— 2.2uF bypass capacitor

— 100mV dropout voltage

 “Wrapper-less” design for optimal timing performance

and design ease

— Low Latency Hi-Speed Receiver (43 Hi-Speed

clocks Max) allows use of legacy UTMI Links with

a ULPI bridge

 Selectable Reference Clock Frequency

— Frequencies: 12, 13, 19.2, 24, 26, 27, 38.4, 52 or

60MHz - pin selectable

 External Reference Clock operation available

— ULPI Input Clock Mode (60MHz sourced by Link)

— 0 to 3.6V input drive tolerant

— Able to accept “noisy” clock sources as reference

to internal, low-jitter PLL

 Internal Oscillator operation available

— This mode requires external Quartz Crystal or

Ceramic Resonator

 Smart detection circuits allow identification of USB

charger, headset, or data cable insertion

 Includes full support for the optional On-The-Go

(OTG) protocol detailed in the On-The-Go

Supplement Revision 2.0 specification

 Supports Headset Audio Mode

 Supports the OTG Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

 UART mode for non-USB serial data transfers

 Internal 5V cable short-circuit protection of ID, DP

and DM lines to VBUS or ground

 Industrial Operating Temperature -40°C to +85°C

 32 pin, QFN Lead-free RoHS Compliant Package

(5 x 5 x 0.90 mm height)

Applications

The USB3320 is targeted for any application where a Hi-

Speed USB connection is desired and when board

space, power, and interface pins must be minimized.

The USB3320 is well suited for:

 Networking

 Audio Video

 Medical

 Industrial Computers

 Printers

 Repeaters

 Communication

Summary of content (82 pages)

PAGE 1
USB3320 Highly Integrated Full Featured Hi-Speed USB 2.
PAGE 2
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet ORDER NUMBER(S): USB3320C-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package USB3320C-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel) Reel size is 4000 pieces. 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved.
PAGE 3
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 0.1 Reference Documents Universal Serial Bus Specification, Revision 2.0, April 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0, May 8, 2009 USB Specification Revision 2.0 "Pull-up/pull-down resistors" ECN (27% Resistor ECN) USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 UTMI+ Specification, Revision 1.
PAGE 4
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table of Contents 0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 USB3320 Pin Locations and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.
PAGE 5
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.2 6.3 6.4 6.5 6.6 6.7 6.1.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 ULPI Interface Timing in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ULPI Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.
PAGE 6
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet List of Figures Figure 1.1 Figure 2.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 5.8 Figure 5.9 Figure 5.10 Figure 5.11 Figure 5.12 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 6.10 Figure 8.1 Figure 8.2 Figure 8.3 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 USB3320 Block Diagram . . . . . . . . . . . . . . . . . . . .
PAGE 7
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet List of Tables Table 2.1 USB3320 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.
PAGE 8
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 1 General Description The SMSC USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution and is an excellent match for a wide variety of products. Both commercial and industrial temperature applications are supported. The frequency of the reference clock is user selectable.
PAGE 9
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used to generate 3.3V from power applied at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout voltage is less than 100mV which allows the transceiver to continue USB signaling when the voltage on VBAT drops to 3.1V.
PAGE 10
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 2 USB3320 Pin Locations and Definitions 2.1 USB3320 Pin Locations and Descriptions 2.1.1 Package Diagram with Pin Locations VDDIO DIR VDD18 STP VDD18 RESETB REFCLK XO 32 31 30 29 28 27 26 25 The illustration below is viewed from the top of the package.
PAGE 11
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 2.1 USB3320 Pin Description (continued) DIRECTION/ TYPE ACTIVE LEVEL NXT Output, CMOS High The transceiver asserts NXT to throttle the data. When the Link is sending data to the transceiver, NXT indicates when the current byte has been accepted by the transceiver. The Link places the next byte on the data bus in the following clock cycle. 3 DATA[0] I/O, CMOS N/A ULPI bi-directional data bus.
PAGE 12
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 2.1 USB3320 Pin Description (continued) DIRECTION/ TYPE ACTIVE LEVEL CPEN Output, CMOS N/A External 5V supply enable. Controls the external VBUS power switch. CPEN is low on POR. 18 DP I/O, Analog N/A D+ pin of the USB cable. 19 DM I/O, Analog N/A D- pin of the USB cable. 20 VDD33 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability.
PAGE 13
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 2.1 USB3320 Pin Description (continued) DIRECTION/ TYPE ACTIVE LEVEL STP Input, CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the transceiver, STP indicates the last byte of data was on the bus in the previous cycle. 30 VDD18 Power N/A External 1.8V Supply input pin. This pad needs to be bypassed with a 0.
PAGE 14
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 3 Limiting Values 3.1 Absolute Maximum Ratings Table 3.1 Absolute Maximum Ratings PARAMETER SYMBOL VBUS, VBAT, ID, CPEN, DP, DM, SPK_L, and SPK_R voltage to GND VMAX_5V Maximum VDD18 voltage to Ground VMAX_18V Maximum VDDIO voltage to Ground VMAX_IOV Maximum VDDIO voltage to Ground VMAX_IOV Maximum VDD33 voltage to Ground CONDITIONS MIN Voltage measured at pin. VBUS tolerant to 30V with external RVBUS.
PAGE 15
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 4 Electrical Characteristics The following conditions are assumed unless otherwise specified: VVBAT = 3.1 to 5.5V; VDD18 = 1.6 to 2.0V; VDDIO = 1.6 to 2.0V; VSS = 0V; TA = -40°C to +85°C The current for 3.3V circuits is sourced at the VBAT pin, except when using an external 3.3V supply as shown in Figure 5.7. 4.1 Operating Current Table 4.
PAGE 16
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.2 Clock Specifications Table 4.2 ULPI Clock Specifications PARAMETER SYMBOL Suspend Recovery Time Note 4.3 TSTART CONDITIONS MIN TYP MAX UNITS 26MHz REFCLK 1.03 2.28 ms 12MHz REFCLK 2.24 3.49 ms 52MHz REFCLK 0.52 1.77 ms 24MHz REFCLK 1.12 2.37 ms 19.2MHz REFCLK 1.40 2.65 ms 27MHz REFCLK 1.00 2.25 ms 38.4MHz REFCLK 0.70 1.95 ms 13MHz REFCLK 2.07 3.32 ms 0.45 0.
PAGE 17
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.4 Digital IO Pins Table 4.4 Digital IO Characteristics: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK Pins PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low-Level Input Voltage VIL VSS 0.4 * VDDIO V High-Level Input Voltage VIH 0.68 * VDDIO VDDIO V High-Level Input Voltage REFCLK only VIH 0.68 * VDD18 VDD33 V Low-Level Output Voltage VOL IOL = 8mA 0.
PAGE 18
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER High Level Output Voltage SYMBOL CONDITIONS MIN TYP MAX UNITS VFSOH Pull-down resistor on DP, DM; Note 4.6 RL = 15kΩ to GND 2.8 3.6 V Driver Output Impedance for HS and FS ZHSDRV Steady state drive 40.5 49.5 Ω Input Impedance ZINP RX, RPU, RPD disabled 1.0 Pull-up Resistor Impedance RPU Bus Idle, Note 4.5 0.900 1.24 1.
PAGE 19
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Port Capacitance Transceiver Input Capacitance CIN Pin to GND 5 10 pF Note 4.5 The resistor value follows the 27% Resistor ECN published by the USB-IF. Note 4.6 The values shown are valid when the USB RegOutput bits in the USB IO & Power Management register are set to the default value. Note 4.
PAGE 20
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.7 OTG Electrical Characteristics Table 4.7 OTG Electrical Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SessEnd trip point VSessEnd 0.2 0.5 0.8 V SessVld trip point VSessVld 0.8 1.4 2.0 V VbusVld trip point VVbusVld 4.4 4.58 4.75 V A-Device Impedance RIdGnd 100 kΩ ID Float trip point VIdFloat VBUS Pull-Up RVPU VBUS Pull-down Maximum A device Impedance to ground on ID pin 1.9 2.
PAGE 21
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.9 Regulator Output Voltages and Capacitor Requirement Table 4.9 Regulator Output Voltages and Capacitor Requirement PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Regulator Output Voltage VDD33 6V > VBAT > 3.1V 3.0 3.3 3.6 V Regulator Output Voltage VDD33 USB UART Mode & UART RegOutput[1:0] = 01 6V > VBAT > 3.1V 2.7 3.0 3.
PAGE 22
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.10 Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section 5.4.1.2. See Table 4.11 for the recommended crystal specifications. See Table 4.12 for the ceramic resonator part numbers for commercial temperature applications.
PAGE 23
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 5 Architecture Overview The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this diagram are connected internally to the VDD33 pin.
PAGE 24
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet it may be desirable to compensate for loss by adjusting the HS transmitter amplitude. The Boost bits in the HS TX Boost register may be configured to adjust the HS transmitter amplitude at the DP and DM pins. 5.2.2 Termination Resistors The USB3320 transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.
PAGE 25
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 5.1 DP/DM Termination vs.
PAGE 26
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.3 Bias Generator This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the USB3320 to minimize the trace length. The nominal voltage at RBIAS is 0.
PAGE 27
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet ~~ VDDIO CLKOUT REFCLK ULPI Clk Out To PLL Link Reference Clk In ~~ Clock Source SMSC PHY Figure 5.2 Configuring the USB332X for ULPI Input Clock Mode (60 MHz) 5.4.1.2 ULPI Output Clock When using ULPI Output Clock Mode, the USB3320 generates the 60MHz ULPI clock used by the Link. The frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Table 5.10. As shown in Figure 5.
PAGE 28
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet ~~ Link ULPI Clk In CLKOUT From PLL REFCLK Internal Oscillator To PLL Resonator XO - or Crystal and Caps SMSC PHY ~~ C LOAD Figure 5.4 ULPI Output Clock Mode After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB3320 is guaranteed to start the clock within the time specified in Table 4.
PAGE 29
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.4.3 REFCLK Jitter The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Input Clock Mode or ULPI Output Clock Mode, the USB3320 Hi-Speed eye diagram may be degraded.
PAGE 30
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet . ~~ VBUS RVBUS VBUS To USB Con. To OTG VBAT VDD33 COUT LDO GND SMSC PHY ~~ Figure 5.6 Powering the USB3320 from a Battery The USB3320 can be powered from an external 3.3V supply as shown below in Figure 5.7. When using the external supply, both the VBAT and VDD33 pins are connected together. The bypass capacitor, CBYP, is recommended when using the external supply. ~~ VBUS RVBUS VBUS To USB Con. Vdd 3.
PAGE 31
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet For peripheral only or host only operation, the VBAT supply shown below in Figure 5.8 may be connected to the VBUS pin of the USB connector for bus powered applications. In this configuration, external overvoltage protection is required to protect the VBAT supply from any transient voltage present at the VBUS pin of the USB connector. The VBAT input must never be exposed to a voltage that exceeds VVBAT. (See Table 3.
PAGE 32
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 5.3 Operating Mode vs. Power Supply Configuration VDD33 VDD18 RESETB OPERATING MODES AVAILABLE 0 0 0 Powered Off 0 1 0 RESET Mode. 0 1 1 In this configuration the ULPI interface is available and can be programed into all operating modes described in Chapter 6. All USB signals will read 0.
PAGE 33
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet T0 SUPPLIES STABLE T1 T2 REFCLK REFCLK valid RESETB DATA[7:0] PHY Tri-States PHY Drives Idle DIR PHY Tri-States PHY Drives High STP IDLE RXCMD IDLE LINK Drives Low TSTART Figure 5.9 ULPI Start-up Timing 5.6 USB On-The-Go (OTG) The USB3320 provides full support for USB OTG protocol. OTG allows the USB3320 to be dynamically configured as a host or device depending on the type of cable inserted into the receptacle.
PAGE 34
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet ~~ VDD33 ID To USB Con. RID=100K RIDW>1M IdPullup IdGnd Vref IdGnd en IdGndDrv IdGnd Rise or IdGnd Fall IdFloat Vref IdFloat en Rid ADC IdFloatRise or IdFloatFall RidValue OTG Module ~~ Figure 5.10 USB3320 ID Resistor Detection Circuitry 5.6.1.1 USB OTG Operation The USB3320 can detect ID grounded and ID floating to determine if an A or B cable has been inserted.
PAGE 35
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 5.4 Valid Values of ID Resistance to Ground ID RESISTANCE TO GROUND RID VALUE Ground 000 75Ω +/-1% 001 102kΩ +/-1% 010 200kΩ+/-1% 011 440kΩ +/-1% 100 Floating 101 Note: IdPullUp = 0 The Rid resistance can be read while the USB3320 is in Synchronous Mode. When a resistor to ground is attached to the ID pin, the state of the IdGnd comparator will change.
PAGE 36
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Note: The IdGnd switch has been provided to ground the ID pin for future applications. 5.6.2 VBUS Monitor and Pulsing The USB3320 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd comparators shown in Figure 5.11 are fully integrated into the USB3320.
PAGE 37
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.6.2.2 SessVld Comparator The SessVld comparator is used when the transceiver is configured as both an A and B device. When configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When configured as a B device, SessVld is used to detect the presence of VBUS.
PAGE 38
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.6.2.4 VBUS Pulsing with Pull-up and Pull-down Resistors In addition to the internal VBUS comparators, the USB3320 also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage so that a Session Request can begin, the USB3320 provides a pull-down resistor from VBUS to Ground.
PAGE 39
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet For example, protecting a peripheral or device only application to 15V would require a 10kΩ RVBUS resistor with a power rating of 0.01W. To protect an OTG product to 15V would require a 1kΩ RVBUS resistor with a power rating of 0.1W. 5.6.3 Driving External VBUS The USB3320 monitors VBUS as described in VBUS Monitor and Pulsing. For OTG and Host applications, the system is required to source 5 volts on VBUS.
PAGE 40
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 5.8 USB Weak Pull-up Enable RESETB DP PULLUP ENABLE DM PULLUP ENABLE 0 0 0 1 ChargerPullupEnableDP ChargerPullupEnableDM Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power Management register. 5.9 USB Audio Support Note: The USB3320 supports “USB Digital Audio” through the USB protocol in ULPI and USB Serial modes described in Section 6.
PAGE 41
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.10 Reference Frequency Selection The USB3320 is configured for the desired reference frequency by the REFSEL[2], REFSEL[1] and REFSEL[0] pins. If a pin is connected to VDDIO, the value of “1” is assigned. Connect the pin to ground to assign a “0.” When using the ULPI Input Clock Mode (60MHz REFCLK Mode), the reference frequency is always fixed at 60 MHz. Eight reference clock frequencies are available as described in Table 5.
PAGE 42
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 6 ULPI Operation 6.1 Overview The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Transceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB Transceiver to an ASIC or digital controller.
PAGE 43
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet low latency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification. RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3320 uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks.
PAGE 44
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor transceiver drive the data bus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and the transceiver will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the transceiver to throttle the USB transmit data is needed.
PAGE 45
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 6.2 ULPI TXD CMD Byte Encoding COMMAND NAME CMD BITS[7:6] CMD BITS[5:0] Idle 00b 000000b ULPI Idle Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID) 00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P3P2P1P0 where P3 is the MSB.
PAGE 46
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet register data. At T4, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register and the Link will pull STP low. NXT is used to control when the Link drives the register data on the bus.
PAGE 47
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.2.2 ULPI Register Read A ULPI register read operation is given in Figure 6.5. The Link drives a TXD CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address. T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD reg read Turn around Reg Data Turn around Idle DIR STP NXT Figure 6.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] TXD CMD extended reg read Idle Extended address Turn around Reg Data Turn around Idle DIR STP NXT Figure 6.6 ULPI Extended Register Read in Synchronous Mode 6.2.3 ULPI RXCMD The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], rxactive, rxvalid and rxerror.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 6.3 ULPI RX CMD Encoding DATA[7:0] NAME DESCRIPTION AND VALUE [1:0] Linestate UTMI Linestate Signals Note 6.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Several important functions for a device and host are designed into the transmitter blocks. The USB3320 transmitter will transmit a 32-bit long high speed sync before every high speed packet. In full and low speed modes a 8-bit sync is transmitted.
PAGE 51
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.2.4.5 No SYNC and EOP Generation (OpMode = 11) UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the ULPI specification and not implemented in the USB3320. 6.2.4.6 Typical USB Transmit with ULPI Figure 6.7 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TXD CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID.
PAGE 52
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet CLK DATA[7:0] Idle Turn around Rxd Cmd PID D1 Rxd Cmd D2 Turn around DIR STP NXT Figure 6.8 ULPI Receive in Synchronous Mode In Figure 6.8 the transceiver asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link.
PAGE 53
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float. 6.3.1 Entering Low Power/Suspend Mode To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control register. After this write is complete, the transceiver will assert DIR high and after a minimum of five rising edges of CLKOUT, drive the clock low.
PAGE 54
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Note 6.2 LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1).
PAGE 55
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.3.3.1 Start up Protection Upon start-up, when the transceiver de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up.
PAGE 56
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled. 6.4 Full Speed/Low Speed Serial Modes The USB3320 includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the Interface control register.
PAGE 57
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.4.0.2 6Pin FS/LS Serial Mode Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.6. Table 6.6 Pin Definitions in 6 Pin Serial Mode SIGNAL CONNECTED TO DIRECTION tx_enable DATA[0] IN Active High transmit enable. tx_data DATA[1] IN Tx differential data on DP/DM when tx_enable is high. tx_se0 DATA[2] IN Tx SE0 on DP/DM when tx_enable is high.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.5.1 USB UART Mode The USB3320 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written before the CarkitMode bit. Table 6.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.5.2 USB Audio Mode When the USB3320 is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete, the USB3320 will immediately enable or disable the audio switch. Then the Link can set the CarkitMode bit in the Interface Control register.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet The ULPI interface is redefined as shown in Table 6.10 when Headset Audio Mode is entered. Table 6.10 Pin Definitions in Headset Audio Mode SIGNAL CONNECTED TO DIRECTION DESCRIPTION SessVld DATA[0] OUT Output of SessVld comparator VbusVld DATA[1] OUT Output of VbusVld Comparator (interrupt must be enabled) IdGndDrv DATA[2] IN Drives ID pin to ground when asserted 0b: Not connected 1b: Connects ID to ground.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 7 ULPI Register Map 7.1 ULPI Register Array The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB3320 ULPI register set is shown in Table 7.1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section 5.5.2.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 7.1 ULPI Register Map (continued) ADDRESS (6BIT) DEFAULT STATE REGISTER NAME READ WRITE SET CLEAR Reserved 00h Vendor Rid Conversion 00h 36-38h 36h 37h 38h USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh Reserved 00h Note 7.1 7.1.1 34-35h 3C-3Fh Dynamically updates to reflect current status of interrupt sources. ULPI Register Set The following registers are used for the ULPI interface. 7.1.1.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT Product ID High 7:0 rd 00h 7.1.1.5 DESCRIPTION SMSC Product ID Function Control Address = 04-06h (read), 04h (write), 05h (set), 06h (clear) FIELD NAME BIT ACCESS DEFAULT XcvrSelect[1:0] 1:0 rd/w/s/c 01b Selects the required transceiver speed.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION ClockSuspendM 3 rd/w/s/c 0b Enables Link to turn on 60MHz CLKOUT in Serial Mode or Carkit Mode. 0b: Disable clock in serial or Carkit Mode. 1b: Enable clock in serial or Carkit Mode. AutoResume 4 rd/w/s/c 0b Only applicable in Host mode. Enables the transceiver to automatically transmit resume signaling. This function is detailed in Section 6.2.4.4.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION DrvVbusExternal 6 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbus. 0b: Do not drive Vbus, CPEN driven low. 1b: Drive Vbus, CPEN driven high. UseExternalVbus Indicator 7 rd/w/s/c 0b Tells the transceiver to use an external VBUS overcurrent or voltage indicator. This function is detailed in Section 5.6.2.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT Reserved 7:5 rd 000b 7.1.1.10 DESCRIPTION Read only, 0. USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. FIELD NAME BIT HostDisconnect 0 VbusValid 1 SessValid ACCESS DEFAULT DESCRIPTION 0b Current value of the UTMI+ Hi-Speed Hostdisconnect output. Applicable only in host mode.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 7.1.1.12 Debug Address = 15h (read only) FIELD NAME BIT ACCESS DEFAULT Linestate0 0 rd 0b Contains the current value of Linestate[0]. Linestate1 1 rd 0b Contains the current value of Linestate[1]. Reserved 7:2 rd 000000b 7.1.1.13 DESCRIPTION Read only, 0. Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) FIELD NAME BIT ACCESS DEFAULT Scratch 7:0 rd/w/s/c 00h 7.1.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet If using USB UART mode the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or MicEn switches are enabled. The USB single-ended receivers described in Section 5.2.1 are disabled when either SpkLeftEn, SpkRightEn, or MicEn are set. 7.1.2.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT RidValue 5:3 rd 000b DESCRIPTION Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 102K ohms 011: 200K ohms 100: 440K ohms 101: ID floating 111: Error Note: RidConversionDone 6 rd 0b Automatically asserted by the USB3320 when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 7.1.3 Vendor Register Access The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3.1 HS TX Boost Address = 31h (read / write) FIELD NAME BIT ACCESS DEFAULT Reserved 4:0 rd 00000b Boost 6:5 rd/w 00b Sets the HS transmitter amplitude as described in Section 5.2.1. 00b: Nominal 01b: Enables 11.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME RidConversionDone BIT ACCESS DEFAULT 3 rd (Note 7.4) 0b DESCRIPTION Automatically asserted by the USB3320 when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status Register will not clear either RidConversionDone status bit.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME ChargerPullupEnDM USB RegOutput Revision 1.0 (07-14-09) BIT ACCESS DEFAULT 5 rd/w/s/c 0b Enables a Pull-up for USB Charger Detection when set on the DM pin. (The pull-up is automatically enabled in UART mode) 7:6 rd/w/s/c 00b Controls the output voltage of the VBAT to VDD33 regulator in USB mode.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 8 Application Notes 8.1 Application Diagram The USB3320 requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this voltage, and the USB3320 provides an integrated overvoltage protection circuit.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet VDDIO Supply RVBUS must be installed to enable overvoltage protection of the VBUS pin. 14 11 8 RVBUS 3.1-5.5V Supply The capacitor CVBUS must be installed on this side of RVBUS.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet VDDIO Supply RVBUS must be installed to enable overvoltage protection of the VBUS pin. 14 11 8 RVBUS 3.1-5.5V Supply The capacitor CVBUS must be installed on this side of RVBUS.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet VDDIO Supply VBUS Switch EN 5V IN OUT The capacitor CVBUS must be installed on this side of RVBUS. RVBUS must be installed to enable overvoltage protection of the VBUS pin.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 8.3.1 Human Body Model (HBM) Performance HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. All pins on the USB3320 except the REFCLK, SPK_L, and SPK_R pins provide ±8kV HBM protection, as shown in Table 4.10. 8.3.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 9 Package Outline, Tape & Reel Drawings, Package Marking The USB3320 is offered in a compact 32 pin lead-free QFN package. Figure 9.1 USB3320 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) Table 9.1 32 Terminal QFN Package Parameters A A1 A2 A3 D D1 D2 E E1 E2 L e b ccc MIN 0.70 0 ~ 4.85 4.55 3.15 4.85 4.55 3.15 0.30 0.18 ~ NOMINAL ~ 0.02 ~ 0.20 REF 5.0 ~ 3.3 5.0 ~ 3.3 ~ 0.50 BSC 0.25 ~ MAX 1.00 0.05 0.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Figure 9.2 QFN, 5x5 Taping Dimensions and Part Orientation SMSC USB3320 79 DATASHEET Revision 1.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Figure 9.3 Reel Dimensions for 12mm Carrier Tape Revision 1.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Figure 9.4 Tape Length and Part Quantity Note: Standard reel size is 4000 pieces per reel. Figure 9.5 Package Marking SMSC USB3320 81 DATASHEET Revision 1.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 10 Revision History Table 10.1 Customer Revision History REVISION LEVEL & DATE Rev. 1.0 (07-14-09) Revision 1.