Datasheet

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
SMSC USB3300 31 Revision 1.1 (01-24-13)
DATASHEET
6.1.5.1 ULPI Register Write
A ULPI register write operation is given in Figure 6.4. The TXD command with a register write
DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the
TXD CMD byte.
To write to a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the databus.
At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register
data. At T4 the PHY will accept the register data and the Link will drive an Idle on the bus and drive
STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the register
and drive NXT low. The Link will pull STP low.
NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this
transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data
is registered after the de-assertion of STP. After the write operation completes, the Link must drive a
ULPI Idle (00h) on the data bus or the USB3300 may decode the bus value as a ULPI command.
Register Write 10b XXXXXXb Immediate Register Write Command where
DATA[5:0] = 6-bit register address
Register Read 11b XXXXXXb Immediate Register Read Command where
DATA[5:0] = 6-bit register address
Figure 6.4 ULPI Register Write
Table 6.4 ULPI TXD CMD Byte Encoding (continued)
COMMAND NAME
CMD
BITS[7:6] CMD BITS[5:0] COMMAND DESCRIPTION
DIR
CLK
DATA[7:0]
STP
NXT
TXD CMD
(reg write)
Idle Reg Data[n] Idle
ULPI Register
Reg Data [n-1] Reg Data [n]
T0 T1 T2 T3 T5T4 T6