Datasheet

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

Revision 1.1 (01-24-13) 24 SMSC USB3300

DATASHEET

Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the data

bus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and the PHY

will not read the data bus.

Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB

transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the

databus by the Link layer.

6.1.3 ULPI Interface Timing

The control and data timing relationships are given in Figure 6.3, "ULPI Timing Diagram" and Ta ble 6.2,

"ULPI Interface Timing". The USB300 PHY provides CLKOUT and all timing is relative to the rising

clock edge. The timing relationships detailed below apply to Synchronous Mode only.

Note: V

DD3.3

= 3.0 to 3.6V; V

= 0V; T

= -40C to 85C; unless otherwise specified.

6.1.4 ULPI Register Array

The USB3300 PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification.

The complete USB3300 ULPI register set is shown in Table 6.3, "ULPI Register Map". All registers are

8 bits. This table also includes the default states of the register upon POR. The RESET bit in the

Figure 6.3 ULPI Timing Diagram

Table 6.2 ULPI Interface Timing

PARAMETER SYMBOL MIN MAX UNITS

Setup time (control in, 8-bit data in) T

5.0 ns

Hold time (control in, 8-bit data in) T

, T

0ns

Output delay (control out, 8-bit data out) T

, T

2.0 5.0 ns

Clock Out -

CLKOUT

Control In -

STP

Data In -

DATA[7:0]

Control Out -

DIR, NXT

Data Out -

DATA[7:0]