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SMSC USB3300 Revision 1.1 (01-24-13)

DATASHEET

Datasheet

PRODUCT FEATURES

USB3300

Hi-Speed USB Host, Device or OTG PHY

with ULPI Low Pin Interface

 USB-IF Hi-Speed certified to the Universal Serial Bus

Specification Rev 2.0

 Interface compliant with the ULPI Specification

revision 1.1 in 8-bit mode

 Industry standard UTMI+ Low Pin Interface (ULPI)

Converts 54 UTMI+ signals into a standard 12 pin

Link controller interface

 54.7mA Unconfigured Current (typical) - ideal for bus

powered applications

 83uA suspend current (typical) - ideal for battery

powered applications

 Latch-Up performance exceeds 150 mA per

EIA/JESD 78, Class II

 ESD protection levels of ±8kV HBM without external

protection devices

 Integrated protection to withstand IEC61000-4-2 ESD

tests (

±8kV contact and ±15kV air) per 3rd party test

facility

 Supports FS pre-amble for FS hubs with a LS device

attached (UTMI+ Level 3)

 Supports HS SOF and LS keep-alive pulse

 Includes full support for the optional On-The-Go

(OTG) protocol detailed in the On-The-Go

Supplement Revision 1.0a specification

 Supports the OTG Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

 Allows host to turn VBUS off to conserve battery

power in OTG applications

 Supports OTG monitoring of VBUS levels with

internal comparators. Includes support for an external

VBUS or fault monitor.

 Low Latency Hi-Speed Receiver (43 Hi-Speed clocks

Max) allows use of legacy UTMI Links with a ULPI

wrapper

 Integrated Pull-up resistor on STP for interface

protection allows a reliable Link/PHY start-up with

slow Links (software configured for low power)

 Internal 1.8 volt regulators allow operation from a

single 3.3 volt supply

 Internal short circuit protection of ID, DP and DM

lines to VBUS or ground

 Integrated 24MHz Crystal Oscillator supports either

crystal operation or 24MHz external clock input

 Internal PLL for 480MHz Hi-Speed USB operation

 Industrial Operating Temperature -40°C to +85°C

 32 pin, QFN lead-free RoHS Compliant package

(5 x 5 x 0.90 mm height)

Applications

The USB3300 is the ideal companion to any ASIC, SoC

or FPGA solution designed with a ULPI Hi-Speed USB

host, peripheral or OTG core.

The USB3300 is well suited for:

 Cell Phones

 PDAs

 MP3 Players

 Scanners

 External Hard Drives

 Digital Still and Video Cameras

 Portable Media Players

 Printers

Summary of content (59 pages)

PAGE 1
USB3300 Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface PRODUCT FEATURES               Datasheet USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0 Interface compliant with the ULPI Specification revision 1.1 in 8-bit mode Industry standard UTMI+ Low Pin Interface (ULPI) Converts 54 UTMI+ signals into a standard 12 pin Link controller interface 54.
PAGE 2
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Order Number(s): USB3300-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package USB3300-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel) Reel Size is 4000 pieces. This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs Copyright © 2013 SMSC or its subsidiaries. All rights reserved.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 0.1 Reference Documents  Universal Serial Bus Specification, Revision 2.0, April 27, 2000  On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003  USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000  UTMI+ Specification, Revision 1.0, February 2, 2004  UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 SMSC USB3300 3 DATASHEET Revision 1.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table of Contents 0.1 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 9 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SMSC USB3300 5 DATASHEET Revision 1.
PAGE 6
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 3.1 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 6.10 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 8.1 Figure 8.1 Figure 8.2 Figure 8.3 Basic ULPI USB Device Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ULPI Interface Features as Related to UTMI+ . . . . . .
PAGE 7
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet List of Tables Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.
PAGE 8
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 1 General Description The USB3300 is an industrial temperature Hi-Speed USB Physical Layer Transceiver (PHY). The USB3300 uses a low pin count interface (ULPI) to connect to a ULPI compliant Link layer. The ULPI interface reduces the UTMI+ interface from 54 pins to 12 pins using a method of in-band signaling and status byte transfers between the Link and PHY. This PHY was designed from the start with the ULPI interface.
PAGE 9
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface ADDED FEATURES Datasheet ULPI Hi-Speed Peripheral, host controllers, On-theGo devices with 12 pin interface (HS, FS, LS, preamble packet) USB3300 UTMI+ Level 3 Hi-Speed Peripheral, host controllers, Onthe-Go devices (HS, FS, LS, preamble packet) USB3500 USB3450 UTMI+ Level 2 Hi-Speed Peripheral, host controllers, Onthe-Go devices (HS, FS, and LS but no preamble packet) UTMI+ Level 1 Hi-Speed Peripheral, host controllers, and On-the-Go d
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 2 Functional Overview VDD3.3 Internal Regulator & POR m 24 MHz XTAL EXTVBUS XO XI VDDA1.8 VDD1.8 The USB3300 is a highly integrated USB PHY. It contains a complete Hi-Speed USB 2.0 PHY with the ULPI industry standard interface to support fast time to market for a USB product. The USB3300 is composed of the functional blocks shown in Figure 2.1 below.
PAGE 11
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 3 Pin Layout The USB3300 is offered in a 32 pin QFN package (5 x 5 x 0.9mm). The pin definitions and locations are documented below. RBIAS REG_EN VDD3.3 VDDA1.8 XI XO VDD1.8 VDD3.3 31 30 29 28 27 26 25 USB3300 Pin Diagram 32 3.1 GND 1 24 DATA0 GND 2 23 DATA1 CPEN 3 22 DATA2 VBUS 4 21 DATA3 ID 5 20 DATA4 VDD3.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) DIRECTION, TYPE ACTIVE LEVEL VBUS I/O, Analog N/A VBUS pin of the USB cable. The USB3300 uses this pin for the Vbus comparator inputs and for Vbus pulsing during session request protocol. 5 ID Input, Analog N/A ID pin of the USB cable. For non-OTG applications this pin can be floated. For an A-Device ID = 0. For a B-Device ID = 1. 6 VDD3.3 Power N/A 3.
PAGE 13
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) PIN NAME DIRECTION, TYPE ACTIVE LEVEL 16 VDD3.3 Power N/A A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB. 17 DATA[7] I/O, CMOS, Pull-low N/A 18 DATA[6] I/O, CMOS, Pull-low N/A 8-bit bi-directional data bus. Bus ownership is determined by DIR.
PAGE 14
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) PIN NAME DIRECTION, TYPE ACTIVE LEVEL 30 VDD3.3 Power N/A Analog 3.3 volt supply. A 0.1uF low ESR bypass capacitor connected to the ground plane of the PCB is recommended. 31 REG_EN I/O, CMOS, Pull-low N/A On-Chip 1.8V regulator enable. Connect to ground to disable both of the on chip (VDDA1.8 and VDD1.8) regulators.
PAGE 15
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 4 Operational Description Table 4.1 Maximum Guaranteed Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum VBUS, ID, EXTVBUS, DP, and DM voltage to GND VMAX_5V -0.5 +5.5 V Maximum VDD1.8 and VDDA1.8 voltage to Ground VMAX_1.8V -0.5 2.5 V Maximum 3.3V supply voltage to Ground VMAX_3.3V -0.5 4.0 V Maximum I/O voltage to Ground VMAX_IN -0.5 4.
PAGE 16
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 5 Electrical Characteristics Table 5.1 Electrical Characteristics: Supply Pins PARAMETER SYMBOL CONDITIONS TYP MAX UNITS Unconfigured Current IAVG(UCFG) Device Unconfigured Same as Idle mA FS Idle 3.3V Current IAVG(FS33) FS idle not data transfer 18.8 21.9 mA FS Idle 1.8V Current IAVG(FS18) FS idle not data transfer 36.4 43.2 mA FS Transmit 3.
PAGE 17
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 5.3 DC Electrical Characteristics: Logic Pins PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low-Level Input Voltage VIL VSS 0.8 V High-Level Input Voltage VIH 2.0 VDD3.3 V Low-Level Output Voltage VOL IOL = 8mA 0.4 V High-Level Output Voltage VOH IOH = -8mA Input Leakage Current ILI Pin Capacitance Cpin VDD3.3 - 0.4 V ±10 uA 4 pF Note: VDD3.3 = 3.0 to 3.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 5.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER Differential Rise/Fall Time Matching SYMBOL FRFM CONDITIONS MIN Excluding the first transition from IDLE state 90 TYP MAX UNITS 111.1 % HS Output Driver Timing Differential Rise Time THSR 500 ps Differential Fall Time THSF 500 ps Driver Waveform Requirements Eye pattern of Template 1 in USB 2.
PAGE 20
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 5.1 Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section 6.3. See Table 5.8 for the recommended crystal specifications. See Table 5.9 for the ceramic resonator part number for commercial temperature applications.
PAGE 21
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 6 Architecture Overview VDD3.3 Internal Regulator & POR XTAL & PLL CPEN EXTVBUS XO XI VDDA1.8 VDD1.8 The USB3300 architecture can be broken down into the following blocks shown in Figure 6.1, "Simplified USB3300 Architecture" below. OTG Module VBUS ID Rpu_dp Rpu_dm Rpd_dp Rpd_dm VDD3.3 DATA[7:0] HS XCVR CLKOUT STP ULPI Digital DP DM Resistors DIR NXT FS/LS XCVR Bias Gen. RBIAS USB3300 Figure 6.
PAGE 22
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.1 Overview Figure 6.2 illustrates the block diagram of the ULPI digital functions. It should be noted that this PHY does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies. The advantage of a “wrapper less” architecture is that the PHY has a lower USB latency than a design which must first register signals into the PHY’s wrapper before the transfer to the PHY core.
PAGE 23
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet In Figure 6.2, "ULPI Digital Block Diagram", a single ULPI Protocol Block decodes the ULPI 8-bit bidirectional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB3300 is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array. 6.1.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the data bus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and the PHY will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB transmit data is needed.
PAGE 25
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Function Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not listed in this table. Table 6.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.4.3 Product ID Low: Address = 02h (read only) FIELD NAME BIT DEFAULT DESCRIPTION Product ID Low 7:0 04h SMSC Product ID revision A0 6.1.4.4 Vendor ID Low: Address = 03h (read only) FIELD NAME BIT DEFAULT DESCRIPTION Product ID High 7:0 00h SMSC Product ID revision A0 6.1.4.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.4.6 Interface Control: Address = 07-09h (read), 07h (write), 08h (set), 09h (clear) FIELD NAME BIT DEFAULT DESCRIPTION 6-pin FsLsSerialMode 0 0b Changes the ULPI interface to a 6-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. 3-pin FsLsSerialMode 1 0b Changes the ULPI interface to a 3-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode.
PAGE 28
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet FIELD NAME BIT DEFAULT DESCRIPTION DrvVbus 5 0b Used to enable external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbusExternal. 0b: do not drive VBUS 1b: drive VBUS DrvVbusExternal 6 0b Used to enable external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbus.
PAGE 29
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet FIELD NAME BIT DEFAULT DESCRIPTION SessEnd Fall 3 1b Generate an interrupt event notification when SessEnd changes from high to low. IdGnd Fall 4 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 0h Driven low. 6.1.4.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.4.12 Debug Register: Address = 15h (read only) FIELD NAME BIT DEFAULT Linestate0 0 0b Contains the current value of Linestate[0]. Linestate1 1 0b Contains the current value of Linestate[1]. Reserved 7:2 000000b 6.1.4.13 Driven low. Scratch Register: Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) FIELD NAME Scratch 6.1.4.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 6.4 ULPI TXD CMD Byte Encoding (continued) COMMAND NAME CMD BITS[7:6] CMD BITS[5:0] Register Write 10b XXXXXXb Immediate Register Write Command where DATA[5:0] = 6-bit register address Register Read 11b XXXXXXb Immediate Register Read Command where DATA[5:0] = 6-bit register address 6.1.5.1 COMMAND DESCRIPTION ULPI Register Write A ULPI register write operation is given in Figure 6.4.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.5.2 ULPI Register Read A ULPI register read operation is given in Figure 6.5. The Link drives a TXD CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address. T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle Txd Cmd Reg Read Turn around Reg Data Turn around Idle DIR STP NXT Figure 6.5 ULPI Register Read At T0, the Link will place the TXD CMD on the databus.
PAGE 33
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet  during a USB receive when NXT is low.  after STP is asserted during a USB transmit cmd. Table 6.
PAGE 34
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet The USB3300 transmitter will transmit a 32-bit long high speed synch before every high speed packet. In full and low speed modes a 8-bit synch is transmitted. When the device or host needs to chirp for high speed port negotiation, the Opmode Bits=10 will turn off the bit-stuffing and NRZI encoding in the transmitter.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet CLK DATA[7:0] TXDCMD (USBtx) Idle D0 D1 D2 D3 IDLE Turn Around RXD CMD Turn Around DIR NXT STP DP/DM SE0 !SQUELCH SE0 Figure 6.6 ULPI Transmit During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB3300 pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet CLK DATA[7:0] Idle Turn around Rxd Cmd PID D1 Rxd Cmd D2 Turn around DIR STP NXT Figure 6.7 ULPI Receive In Figure 6.7, "ULPI Receive" the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXD CMD data is transferred to the Link.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] TXD CMD (reg write) Idle Reg Data[n] Turn Around Idle ... T10 Low Power Mode DIR STP NXT SUSPENDM (ULPI Register Bit) Figure 6.8 Entering Low Power Mode While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the Vbus voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.9.2 Exiting Low Power Mode To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3300 will begin its start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and de-assert DIR. Once DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode.
PAGE 39
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started. In this case, the USB3300 has an internal pull-up on the STP input pad which will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register.
PAGE 40
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.10.1 3pin FS/LS Serial Mode Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.7, "Pin Definitions in 3 pin Serial Mode". Table 6.
PAGE 41
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet by the Link. The state of the resistors is determined by the operating mode of the PHY. The possible valid resistor combinations are shown in Table 6.8, "DP/DM termination vs. Signaling Mode". Operation is guaranteed in the configurations given in the table below.  RPU_DP_EN activates the 1.5kΩ DP pull-up resistor  RPU_DM_EN activates the 1.
PAGE 42
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 6.8 DP/DM termination vs.
PAGE 43
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.4 Internal Regulators and POR The USB3300 includes an integrated set of built in power management functions, including a POR generator. Internal regulators enable the USB3300 to be powered from a single 3.3 volt power supply, thereby reducing the bill of materials and simplifying product design. 6.4.1 Internal Regulators The USB3300 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet ID R=100K R>1M IdGnd 0.6V IdPullup 0.5V SessEnd VDD33 R>=281 1.4V SessValid R>=656 ChrgVbus 4.575V VbusValid R=75K VBUS DischrgVbus [0, X] [1, 0] EXTVBUS RXCMD VbusValid [1, 1] IndicatorComplement [UseExternalVbusindicator, IndicatorPassThru] DrvVbus CPEN DrvVbusExternal OTG Module Figure 6.
PAGE 45
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet be overpowered and the ID pin will be brought to ground. To save current when a Mini-A Plug is inserted, the ID pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register. To prevent the ID pin from floating to a random value, a weak pull-up resistor is provided at all times. The circuits related to the ID comparator are shown in Figure 6.
PAGE 46
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.5.2.4 Vbus Pull-up and Pull-down Resistors In addition to the internal Vbus comparators the USB3300 also includes the integrated Vbus pull-up and pull-down resistors used for Vbus Pulsing. To discharge the Vbus voltage, so that a Session Request can begin, the USB3300 provides a pull-down resistor from Vbus to Ground.
PAGE 47
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 6.10 External Vbus Indicator Logic (continued) TYPICAL APPLICATION USE EXTERNAL VBUS INDICATOR INDICATOR PASS THRU INDICATOR COMPLEMENT Standard Host 1 1 0 External active high power fault signal 1 1 1 External active low power fault signal 0 X X Internal VbusVld comparator. This should not be used by the Link. (Note 6.2) Standard Peripheral RXCMD VBUS VALID ENCODING SOURCE Note 6.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 7 Application Notes The USB3300 requires few external components as shown in the application diagrams. In some applications, the power supplied on the VBUS and GND pins of the USB connector is used as the source of system power. The USB2.0 standard restricts the voltage at the VBUS pin to a maximum value of 5.25V.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 7.1 Application Diagrams Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS. RVBUS may be installed in this configuration to assist in protecting the VBUS pin. 820 Ohms will protect against VBUS transients up to 8.5V. 10K Ohms will protect against transients up to 10V. RVBUS The capacitor CVBUS must be installed on this side of RVBUS. 3.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS. USB3300 Link Controller 3 CPEN 31 REG_EN 30 VDD3.3 6 VDD3.3 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESET 16 VDD3.3 XO 27 25 VDD3.3 XI 28 VBUS Switch 5V 10 EN FLG IN OUT 4 RVBUS may be installed to assist in protecting the VBUS pin. 820 Ohms will protect against VBUS transients up to 8.5V.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS. Optional Over-voltage Protection The capacitor CVBUS must be installed on this side of RVBUS. 3.3V Supply CBYP USB Receptacle Link Controller USB3300 Over-voltage device may be desired to protect against out-of-spec chargers.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 7.2 Multi-port Applications To support multiple ports a single USB3300 host can be combined with one of SMSC’s many hub products to expand the number of ports. SMSC has 2-port, 3-port, 4-port, and 7-port hub designs which can be used to expand the number of ports in a design.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 7.4.1 Human Body Model (HBM) Performance HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. All pins on the USB3300 provide ±8kV HBM protection. 7.4.
PAGE 54
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 8 Package Outline The USB3300 is offered in a compact 32 pin lead-free QFN package. Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) Table 8.1 32 Terminal QFN Package Parameters A A1 A2 A3 D D1 D2 E E1 E2 L e b ccc MIN 0.70 0 ~ 4.85 4.55 3.15 4.85 4.55 3.15 0.30 0.18 ~ NOMINAL ~ 0.02 ~ 0.20 REF 5.0 ~ 3.3 5.0 ~ 3.3 ~ 0.50 BSC 0.25 ~ MAX 1.00 0.05 0.90 5.15 4.95 3.45 5.15 4.95 3.45 0.
PAGE 55
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Figure 8.1 QFN, 5x5 Taping Dimensions and Part Orientation SMSC USB3300 55 DATASHEET Revision 1.
PAGE 56
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Figure 8.2 Reel Dimensions for 12mm Carrier Tape Revision 1.
PAGE 57
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Figure 8.3 Tape Length and Part Quantity Note: Standard reel size is 4000 pieces per reel. SMSC USB3300 57 DATASHEET Revision 1.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 9 Datasheet Revision History Table 9.1 Customer Revision History Rev. 1.1 (01-24-13) Section 5.1, "Piezoelectric Resonator for Internal Oscillator," on page 20 Added section. Rev. 1.08 (11-07-07) Table 3.1, "USB3300 Pin Definitions 32Pin QFN Package" Description for Pins 15, 26, 29 and 31 modified. Rev. 1.08 (10-25-07) Table 3.
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 9.1 Customer Revision History Rev. 1.05 (05-26-06) Rev 1.04 (02-28-06) Rev. 1.03 (05-11-05) SMSC USB3300 Table 4.1 Added ESD and Latch-up entries Section 7.4 Added Section 7.4 Cover - Features: ESD protection levels of ±8kV HBM without external protection devices Removed mention of wrapper available from SMSC (Also removed from Section 1 and 6.1.1) Added bullets on ESD and latch-up.