Datasheet
Table Of Contents
- Chapter 1 USB251x Hub Family Differences Overview
- Chapter 2 General Description
- Chapter 3 Acronyms
- Chapter 4 Block Diagram
- Chapter 5 Pin Descriptions
- Chapter 6 LED Usage Description
- Chapter 7 Battery Charging Support
- Chapter 8 Configuration Options
- Chapter 9 DC Parameters
- 9.1 Maximum Guaranteed Ratings
- 9.2 Operating Conditions
- Figure 9.1 Supply Rise Time Model
- Table 9.1 DC Electrical Characteristics (continued)
- Table 9.2 Supply Current Unconfigured: Hi-Speed Host (ICCINTHS)
- Table 9.3 Supply Current Unconfigured: Full-Speed Host (ICCINTFS)
- Table 9.4 Supply Current Configured: Hi-Speed Host (IHCH1)
- Table 9.5 Supply Current Configured: Full-Speed Host (IFCC1)
- Table 9.6 USB251x/xi/xA/xAi Supply Current Suspend (ICSBY)
- Table 9.7 USB251xB/xBi Supply Current Suspend (ICSBY)
- Table 9.8 USB251x/xi/xA/xAi Supply Current Reset (ICRST)
- Table 9.9 USB251xB/xBi Supply Current Reset (ICRST)
- Table 9.10 Pin Capacitance for USB251x, USB251xi, USB251xA, USB251xAi
- Table 9.11 Pin Capacitance for USB251xB and USB251xBi
- 9.2.1 Package Thermal Specifications
- Chapter 10 AC Specifications
- Chapter 11 Package Outlines
USB 2.0 Hi-Speed Hub Controller
Datasheet
SMSC USB251x 57 Revision 1.1 (04-26-10)
DATASHEET
USB2513/13i and USB2514/14i Only: The LED_A[x:1]_N pins are sampled after RESET_N negation,
and the logic values are used to configure the hub if the internal default configuration mode is selected.
The implementation shown in Figure 8.5 shows a recommended passive scheme. When a pin is
configured with a "Strap High" configuration, the LED functions with active low signaling, and the PAD
will "sink" the current from the external supply. When a pin is configured with a "Strap Low"
configuration, the LED functions with active high signaling, and the PAD will source the current to the
external LED.
8.7 Reset
There are two different resets that the hub experiences. One is a hardware reset via the RESET_N
pin and the second is a USB Bus Reset.
8.7.1 External Hardware RESET_N
A valid hardware reset is defined as assertion of RESET_N for a minimum of 1 μs after all power
supplies are within operating range. While reset is asserted, the hub (and its associated external
circuitry) consumes less than 500 μA of current from the upstream USB power source.
Assertion of RESET_N (external pin) causes the following:
1. All downstream ports are disabled, and PRTPWR power to downstream devices is removed (unless
BC_EN is enabled).
2. The PHYs are disabled, and the differential pairs will be in a high-impedance state.
3. All transactions immediately terminate; no states are saved.
4. All internal registers return to the default state (in most cases, 00(h)).
5. The external crystal oscillator is halted.
6. The PLL is halted.
The hub is “operational” 500 μs after RESET_N is negated. Once operational, the hub immediately
reads OEM-specific data from the external EEPROM (if the SMBus option is not disabled).
8.7.1.1 RESET_N for Strapping Option Configuration
Figure 8.6 Reset_N Timing for Default/Strap Option Mode
t1
t4
t5
t6
t7 t8
Valid Driven by Hub if strap is an output.
RESET_N
VSS
Strap Pins
VSS
Hardware
reset
asserted
Read Strap
Options
Drive Strap
Outputs to
inactive
levels
Attach
USB
Upstream
USB Reset
recovery
Idle
Start
completion
request
response
t2
t3
Don’t Care
Don’t Care